Fall 2010 – Digital Design C421 Syllabus

Instructor:      Dr. John F. Doyle, P.E.

Office:          LF112 OH: M/W 1500-1800 and by appointment

                           T/R 1530-1630

Class:           Number: 27326, Room: PS014  - T/R 1300-1450 (1pm – 2:50pm)

Phone:           812-941-2195 (Please use email first)

Email:           jfdoyle@ius.edu

Text:            Fundamentals of Digital Logic with VHDL Design. ISBN 0077221435 / 9780077221430

                 Previous Textbook Online Resources

Course Goals

Prerequisites:   C202, C251

Grade Scale:     A+ 97% - 100%     A  93% - 96%        A-  90% - 92%

                 B+ 87% -  89%     B  83% - 86%        B-  80% - 82%

Click for        C+ 77% -  79%     C  73% - 76%        C-  70% - 72%

Grade Book:      D+ 67% -  69%     D  63% - 66%        D-  60% - 62%

                 F  0% -   59%

Course Evaluation: 2 Tests = 40%

Exercises/HW = 30%

Final Exam = 30%

            Total             = 100%

Homework - Due at the start of class.

Project - On designated dates, part of class time will be spent practicing design skills necessary for homework assignments.

Teams - Student teams of two or three will be required for the project and select homework assignments.

Ethics - All graded work is expected to be the product of individual effort and is subject to the Indiana University Code of Student Ethics.

Preliminary/Tentative Class Schedule: [I reserve the right to change this schedule at any time]

   Aug 24   Introduction. Chapter 1 and Chapter 2 Notes.

26   Introduction. Chapter 1 and Chapter 2 Notes.

31   Laboratory Introduction

   Sep 02   Exercises 1 Due

       06   School Holiday (Labor Day)

       07   Read Chapter 3

       09   Exercises 2 Due.

       14   Read Chapter 4 Exercises 3 due

       16   Read Chapter 5

21   Chapter 4 Notes Exercises 4 Due.

       23   Wrap up Chapters 1-4.

       28   Chapter 5 Notes

       30   Chapter 5 Notes

   Oct 05   Chapter 5 Notes,

       07   Chapter 6 Notes. Specification of sequential systems. Exercises 5 Due.

       12   Exam #1 Exercises 6 Due.

       14   Specification of sequential systems

       19   Exercises 7 due.

       21   Chapter 8

       26   Exercises 8 due.

       28   VHDL Code, State Machines

   Nov 02   Exercises 9 due.

       04   TBD

       09   TBD

       11   Exam 2 Exercises 10 due.

       16   TBD

       18   TBD

       23   Thanksgiving Break, no class

       25   Thanksgiving Break, no class

       30   TBD

  Dec  02   Exercises 11 due

       13   Final Exam due at 5:30pm All other work must be submitted at this time as well.

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