Homework 1 - Introduction to Computer Architecture

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Included are assignments on key points from class and text regarding foundational concepts necessary for understanding standard computer operation.


Hypothetical Machine 

Runnion discusses a hypothetical (not real) machine to more easily understand machine operation. The hypothetical machine architecture described in the text is simple enough to be implemented in software by a one page C++ program! The software merely simulates the operation of the hypothetical computer CPU which produces the same results as if the hypothetical CPU existed. Simulating the hypothetical hardware in software is a truly powerful idea since programs can be written for the hypothetical machine but executed by simulation software on a real computer.  See the Hypothetical Machine in C++ at the end of this document for the simulator software. Software for new hardware is often implemented in this way while the hardware is still under development.

How does the simulator or interpreter work? In fact, much like the hardware it simulates, both implement a Fetch/Execute cycle. Suppose we had written the following program instructions:

 Z = Y + 921

The corresponding program would be as in Figure 1.

 

Figure 1

Address  Instruction    Mnemonic        Comments 
000        01005         LDA Y          A = Y
001        20004         ADD 921        A = A + 921
002        02006         STA Z          Z = A
003        30007         Jmp 007        GO TO Address 7
004        00921    921  00921          Constant 921
005        04800    Y    04800          Variable Y
006        00807    Z    00807          Variable Z
007        99000         HLT            Halt Execution
 
 
NOTE: The MNEMONIC column entries correspond to the INSTRUCTION column, so mnemonic Jmp 007 is stored as 30007 (JMP is code 30) at memory ADDRESS 003. Variable Y address is 005 so that mnemonic LDA Y instruction code is 01005 (LDA is code 01 and Y is at address 005). The constant 921 must also be stored in memory, at address 004.

To run this program, the simulator executes the fetch/execute cycle for the hypothetical machine. The execution starts by fetching the LDA Y instruction and executing. The simulator program simply implements the hypothetical machine fetch/execute cycle as below:

ALGORITHM:

Simply stated, a hardware CPU runs a program by repeatedly FETCHING one instruction from memory and EXECUTING that instruction in an endless cycle. This is called the FETCH/EXECUTE cycle. To simulate the hardware CPU, the software simulator must implement this cycle as below.
1.   Fetch instruction at PC by:    MAR = PC
                                    MDR = Memory[ MAR ]
                                    IR  = MDR
2.   PC = PC + 1                    PC = next instruction address
3.   Decode instruction:            OP = IR operation field
                                    Addr = IR address field
4.   Execute operation OP.
5.   Go to 1.
 
DATA:
Notice that the CPU architecture (internal memory: PC, IR, A, B, MDR, MAR) and external memory are simulated using variables to hold each register's data. We accurately represent the hypothetical CPU internal memory by:
PC     3 digits, holds address in range 000 to 999 of next instruction.
IR     5 digits, holds instruction (2-digit operation and 3-digit operand).
A, B   5 digits, holds numerical value in range -99999 to 99999.
MAR    3 digits, holds address in range 000 to 999 of Memory index.
MDR    5 digits, holds numerical value accessed to/from Memory[ MAR ].
Memory 5 digits, array indexed from 000 to 999, holds values -99999 to 99999.


Hypothetical Machine Simulator - Assignment 1

Machine language programs for the hypothetical machine can be executed using a Web-based simulator that executes programs as discussed above. The simulator allows easy modification of memory and CPU registers, step-by-step execution of programs, and observation of internal CPU operations. We will use the simulator to help understand how a CPU executes machine language programs by observing the step-by-step operations performed by the CPU.

A non-interactive simulator is also given below in C++ as an example.

Example

Address    Value
000        01005 
001        20004 
002        02006
003        30007
004        00921
005        04800 
006        00807
007        99000

Assignment 1 Questions

  1. What CPU state starts every FETCH (the CPU state is displayed below the Reset button).
  2. List each CPU state required to perform FETCH/EXECUTE of the instructions:
  3. Instruction 20004 takes longer to execute. Why?
  4. A common CPU power rating is its operational clock speed, for example, a Pentium CPU operating at 100 MHz. roughly meaning that it can perform a state change (not execute an instruction) in one hundred millionth of a second or 100,000,000 state changes per second. Assuming the Hypothetical Machine CPU is rated at 100 MHz., how long will it take to FETCH/EXECUTE each of the following instructions:
  5. Write a Hypothetical machine program in the form of the Sample Program above to implement the expression:
    1.  
      U = (R+6-T)*S
       
    for the values of R=100, S=8, and T = 1.

    Note: Since the multiply instruction generates a 10 digit result and stores the most significant 5 digits in the A register and the least significant 5 digits in the B register, the result is in the B register. To assign variable U the final result, store the value of the B register to variable U. Choose any reasonable addresses for the variables R, S, T and U but note that the constant 6 will also have to be stored at a memory address.

  6. Test your program using the simulator. Print simulator screen showing the value of the variable U memory address (you may want to first minimize the browser similar to the figure above) . Press the Alt Prnt Scrn keys at the same time to capture the screen. Then paste into Word or other word processor and print.

Turn in

  1. Cover sheet with your name, date, Homework 1, Assignment 1. Staple all pages together.
  2. Answers to Assignment 1 Questions, for Question 5 include a listing of your program as in Figure 1.