Chapter 2

Data Representation

Must know number of bits used to represent data. In the following for convenience we'll use just 4 bits to represent numbers.
Signed magnitude, One's and Two's Complement 4-bit numbers
Decimal Signed
Magnitude
One's
Complement
Two's
Complement
0 0000 0000 0000
1 0001 0001 0001
2 0010 0010 0010
3 0011 0011 0011
4 0100 0100 0100
5 0101 0101 0101
6 0110 0110 0110
7 0111 0111 0111
-0 1000 1111  None
-1 1001 1110 1111
-2 1010 1101 1110
-3 1011 1100 1101
-4 1100 1011 1100
-5 1101 1010 1011
-6 1110 1001 1010
-7 1111 1000 1001
-8  None None  1000

ASCII - 

Characters are represented by a code number, the character A is number code 6510 or 4116, or 010000012. Character 7 is number code 5510 or 3716, or 001101112.

Using the Appendix E, page A-115, the character A is in row 4 and column 1 so is code 4116. Character M is in row D16 and column 4 so is code D416.

ASCII chart

  

Data Defining Pseudo Operations

  1. DB - Define Byte data, 8 bits
  2. DW - Define Word data, 16 bits. Stored in reverse byte order. 1234h stored as 34 12.
  3. DD - Define Double word data, 32 bits. Stored in reverse byte order. 12345678h stored as 78 56 34 12.
Example
 
               Data    Segment                     Offset        Contents     
   Offset                                 Memory       0000 0F 00 1B 43 41 42 43 44
     0000        X    Dw    15                         0008 45 01 00 02 00 03 00 09
     0002        Y    Db    27                         0010 09 09 09 09 78 56 34 12
     0003        C    Db    'C'
     0004        Name Db    'ABCDE'
     0009        Z    Dw    1, 2, 3
     000F        A    Db    5 dup(9)
     0014        N    Dd    12345678h
     0018

Constant Definitions

Internal Registers of Intel Processor (Important ones for now)

 

Data Exchange

Stack Operations (Push and Pop)

Push
  • PUSH Operand effect is:
    1. eSP = eSP - 4
    2. [eSP] = Operand
  • Example
  • Mov    eAx, 1234h               Address  Stack Before Push     Stack After Push
    Push   eAx                        0008       0000                 0000
    eAx = 1234                eSP->   0006       0000                 0000
                                      0004       0000                 0000
                                      0002       0000         eSP->   1234

Addressing Modes

Many instructions can have operands that are constants, memory variables, or register variables. The following presents an example for understanding how three of the operand accessing modes work.
  1. Immediate - Example: Mov eDX, 1234h, has 1234x as the operand part of the instruction.
  2. Register - Data source and destination are both registers within the CPU. Mov eDX, eBX, has eDX as the destination register and eBX as the source register.
  3. Direct - One of the operands is a memory location. The instruction  Mov  U,  eAX, has one operand, U, a memory location. The instruction moves the contents of the eAX register value to a memory location,U.

Intel Register Set

The internal memory of the CPU that is accessible by a program are registers. Some are special purpose, used by specific instructions. For example, multiplication always uses the Ax register and the Push and Pop instructions always affect the Stack Pointer. We'll consider the 16-bit processors (internal operations and registers are 16-bit) for simplicity though the concepts apply to current processors. A brief list of those registers of immediate interest and description follows:
  • eAX, eBX, eCX, eDX 32-bit general purpose registers (can be operands in most instructions, Add, Mov, Xchg, etc.)
  • AX, BX, CX, DX - 16-bit general purpose registers (can be operands in most instructions, Add, Mov, Xchg, etc.).
  • AH, AL, BH, BL, CH, CL, DH, DL - The corresponding high and low 8-bits of the AX, BX, CX, DX  registers.
  • eSP - 32-bit stack pointer.
  • eIP - Instruction pointer 32-bit, points to the next instruction to be fetched.

Physical Memory [16 bit, enrichment only]

Physical memory on the Intel 8086 is limited to 220 addresses since the address bus is only 20 bits wide. To access a variable in memory, the stack, or to fetch an instruction requires a 20-bit address. But the stack pointer, Sp, variable operands, and the instruction pointer, Ip, are only 16-bits, not 20-bits, so cannot access all of physical memory directly.

Memory Addressing [16 bit, enrichment only]

Recall that Program = Algorithm + Data. The processor supports several memory models, the segmented memory addressing model used on the PC divides memory into four separate segments for:
  1. program algorithm or code segment - CS
  2. data segment - DS
  3. stack segment - SS
  4. extra segment - ES
The starting location of each segment in memory is determined by the value of the segment registers, Cs, Ds, Es, and Ss.
 
Memory Segments
       CS
Code Segment
(Algorithm)
      ES
Extra Segment
        DS
Data Segment
       SS
Stack Segment

To understand how segmented memory addressing works consider when a memory variable is accessed by the instruction, Mov X, 74h. Assume physical memory, the location of X in the segment, and the Ds register are defined as below. Remember that the DS register points to the start of the Data Segment where X is located. The offset of X is the distance of the location of X from the start of the segment.
 

X offset = 0048h
DS = 1230h
Physical Address X = Ds*10h + offset X = 1230h*10h + 0048h = 12348h
Physical Memory Before Mov X, 34h
20-bit address 8-bit Contents
12345 42
12346 00
12347 00
12348 X 00
12349 00
1234A 00
1234B 19
Physical Memory After
Mov X, 34h
20-bit address 8-bit Contents
12345 42
12346 00
12347 00
12348 X 74
12349 00
1234A 00
1234B 19
Data Segment starts at 12300h when DS=1230h
16-bit Offset 8-bit Contents
0045 42
0046 00
0047 00
0048 X 74
0049 00
004A 00
004B 19
Physical Address Push or Pop = Ss*10h + Sp

Assembly Program Structure [16 bit, enrichment only]

Assembly programs are much like C++, Basic, Pascal, or Cobol programs. The program has data and algorithm definition parts, usually defined in a data and a code segment. A stack segment is often defined also. The algorithm part is made up of one or more procedures or functions. Note that segment and procedure names are arbitrary (i.e. Data, Code, Sseg, Proc1, Proc2 below could be any names). Generally, the program structure is (keywords are boldfaced type):
Data    Segment
        Variable definitions
Data    Ends
Code    Segment
        Assume   CS:Code, DS:Data, SS: Sseg        ;; Associate CS with Code
                                                   ;; DS with Data, SS with Sseg
        Proc1    Proc    Far
                 Algorithm 
        Proc1    Endp
        Proc2    Proc    Far
                 Algorithm 
        Proc2    Endp
 Code   Ends
 Sseg   Segment  STACK
        Db 254 dup(?)    
 Sseg   Ends
 End     Proc2                                     ;; First instruction executed
                                                   ;; is Proc2

Address Accessing Operators and Instructions [16-bit, enrichment only]

When a program is executed, the CS:IP registers must point to the first instruction to be executed, and DS must point to the start of the program data segment. Executing a program from the DOS prompt automatically initializes CS:IP but it is our responsibility to initialize the DS register to the data segment. In the following example we'll use a fragment from HW1 program.
 
   0000			DATA     Segment                    ;;Data Segment 
   0000 0064		 R        DW            100         ;; R = 23
   0002 0008	         S        DW             8          ;; S = 8 
   0004 0001		 T        DW             1          ;; T = 1 
   0006 0000		 U        DW             ?          ;; U is uninitialized
   0008		        DATA     Ends                       ;; End of segment DATA

   0000			ALGORITHM Segment                   ;;Algorithm Segment 
			        Assume   Cs:ALGORITHM, Ds:DATA, Ss:SSeg

   0000			HW1     Proc     Far                ;; Procedure HW1
   0000  BB ---- R	        Mov      Bx, Seg DATA       ;; Initialize DS register 
   0003  8E DB		        Mov      Ds, Bx             ;; to address of data segment

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