Laboratory 3 and Homework 3
Hierarchical Devices and Propagation Delays

• Laboratory 3
• Methods for Hierarchical Digital Design
• Hierarchical Design with VHDL
• Higher level design
• Concurrency and Propagation Delay
• Propagation through Hierarchical Devices
• Hierarchical Design Implementation and Simulation
• Implementing and Simulating the eqbit design
• Implementing and Simulating the eq4 design
• Homework 3
• EQUIPMENT
• ASSIGNMENT
• TURN IN

Laboratory 3

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Methods for Hierarchical Digital Design

Digital design, implementation, and testing methods are similar to those followed by software designers in which more complex, higher level components are constructed from simpler, lower level components. A C++ function, eqbit, to determine if single bit values were the equal, either both true or both false, could be written as below.
 

eqbit function Truth Table	eqbit C++ function
x y e | eq      0 0 0 | 0     0 0 1 | 1     0 1 0 | 0     0 1 1 | 0     1 0 0 | 0     1 0 1 | 0     1 1 0 | 0     1 1 1 | 1	void eqbit( int x, int y, int e, int &eq)  { eq = (x && y && e) || (!x && !y && e);  }

Building on the eqbit, the eq4 function determines if four bit values are equal by repeated execution of the eqbit function. The test data is supplied by the main function which uses the higher level eq4 function. Notice how the calls to the eqbit function are connected, that the output of eqbit(a[0], b[0], s[0], s[1]) is s[1] which is an input to eqbit(a[1], b[1], s[1], s[2]);. The effect is to cascade the function results from one call to the next. The final call of eqbit(a[3], b[3], s[3], equal); connects the eqbit output  with the eq4 output.
 

eq4 function to determine if four bits are equal	Test function
void eq4(int a[4], int b[4], int &equal)  { int s[4];       s[0] = 1;       eqbit(a[0], b[0], s[0], s[1]);       eqbit(a[1], b[1], s[1], s[2]);       eqbit(a[2], b[2], s[2], s[3]);       eqbit(a[3], b[3], s[3], equal);  }	#include <iostream.h>  void main(void)  {   int m[4]={0,0,0,0}, n[4]={0,0,0,1}, equal;     eq4( m, n, equal);     cout << equal;  }

The top down design hierarchy would be 1) main, 2) eq4, and 3) eqbit. There are many motivations for hierarchical design, an obvious one here is the difficulty of designing and implementing eq4 directly since with eight inputs the truth table would have 256 rows!

Hierarchical Design with VHDL

VHDL designs, as in C++, can be done as one large unit or broken into smaller components. Use of external C++ functions require a function prototype to define the function interface and the compiled function code for producing an executable program. The following VHDL implements the same logic as the C++ eqbit function. The ENTITY defines the interface much as a C++ function header. The ARCHITECTURE defines additional signals and the operation of the design, similar to the data definition and executable part of a C++ function.
 

-- File eqbit.vhd -- ENTITY - The interface part of design ENTITY eqbit IS   PORT (x, y, e : IN BIT;                     eq : OUT BIT);  END eqbit;  -- ARCHITECTURE - The implementation part of the design ARCHITECTURE behavioral OF eqbit IS  BEGIN   PROCESS (x, y, e)   BEGIN        eq <= (x AND y AND e) OR (NOT x AND NOT y AND e);   END PROCESS;  END behavioral;

Higher level design

As in the C++ example, it is more efficient to build complex, high level designs based on simpler, lower level ones. The corresponding VHDL must also have a definition of the interface to the eqbit operation. In C++ a function prototype defines the interface, in VHDL a component port serves the same purpose.
 

-- File eq4.vhd -- eq4 uses the eqbit component ENTITY eq4 IS   PORT (a3, a2, a1, a0 : IN BIT;              b3, b2, b1, b0 : IN BIT;                            equal : OUT BIT);  END eq4;  ARCHITECTURE structural OF eq4 IS  -- Define the interface port to eqbit    COMPONENT eqbit                  PORT (x, y, e : IN BIT;   eq : OUT BIT);     END COMPONENT;     SIGNAL s0, s1, s2, s3 : BIT;  BEGIN   s0 <= '1';   U0 : eqbit PORT MAP(a0, b0, s0, s1);                  -- Define signal connections to U0, an eqbit device   U1 : eqbit PORT MAP(a1, b1, s1, s2);   U2 : eqbit PORT MAP(a2, b2, s2, s3);   U3 : eqbit PORT MAP(a3, b3, s3, equal);  END structural;

Concurrency and Propagation Delay

Although the C++ and VHDL have many syntactical similarities, there are fundamental differences. One key difference is that while C++ statements are executed sequentially, one after the other, VHDL statements can be performed concurrently, all are performed at the same time. That makes sense when one considers that VHDL describes electrical circuits in which a signal propagates from the inputs through multiple paths to the output. To illustrate, in the VHDL eq4 there are four eqbit devices used, U0, U1, U2, U3 where the output s1 of U0 is input to U1, the output s2 of U1 is input to U2, etc. This can be seen from a graphical representation of the eq4 design given below.

Notice the eq4 inputs a3-a0 and b3-b0, and the output equal. The connections between each eqbit component U3-U0  is made using the signals or wires s3-s0. Whenever the a3-a0 and b3-b0 inputs change, it takes some time for each eqbit component to change to the proper output. Since eqbit component U3 can't produce a result until all other components below it have a result, U3 takes longer to produce a result due to the propagation introduced by each eqbit component. Simulation below shows the propagation delay clearly for a single eqbit.

The dark area in the simulation shows that when the inputs x = 0, y = 0, e = 0 changed to e = 1, the output eq = 0 changed to eq = 1. However, the change of the output did not occur instantly but was delayed while the input changes propagated  through the eqbit internal gates, recall eq <= (x AND y AND e) OR (NOT x AND NOT y AND e);  so the AND, OR , and NOT gates must change also. The propagation of each device varies, as discussed in the text, dependent upon the specific technology used. Using the MAX+plus II developer, the eqbit device has a propagation delay of 7.5 ns. which is the time interval in the darkened area from when input e changed from 0 to 1 until output eq changed from a 0 to 1.

Propagation through Hierarchical Devices

Generally, the more devices the longer the delay since the total delay is the sum of the delay in each device. Since one eqbit devices had 7.5 ns. delay, the expected delay for a series of four eqbit would be four times or 30 ns. and the maximum delay is the total delay through the longest series of devices. However, due to the technology used, a Field Programmable Gate Array that uses a lookup table to implement a combinational device, the delay times are not easily determined, usually requiring analysis by computer. In the simulation of eq4 device, instead of  the expected 30 ns. total delay from when the inputs change to when the output responds, the delay is 11.5 ns., much better than expected. The simulation shows the change in the darkened area where all inputs are 0 and output equal is 1, then when input a0 changes to 1 output equal, at the end of four eqbit devices, requires 11.5 ns. to change.

One final point, while the text indicates that propagation delays can be specified in VHLD, the MAX+plus II package will not honor delays since it is simulating a known device with known propagation delay characteristics, one of the two Field Programmable Gate Arrays that will be used in later laboratories. The FPGA used by default has a minimum propagation delay of 7.5 ns.

Hierarchical Design Implementation and Simulation

As designs grow more complex with more inputs and outputs, one problem with simulation is entering all possible input values necessary to exhaustively test the design. The simulator offers some useful tools to group inputs and outputs together and to control the time between changes on the inputs. Another skill is how to implement a hierarchical design having multiple files. The following offers practice in both using the eqbit and eq4 designs. The steps are:

Implementing and Simulating the eqbit design

1. Enter the eqbit file by copying code with a browser or typing it in. In MAX+plus II enter File, New, Text File from the menus and enter the design. Save as eqbit.vhd.
2. Click  to make eqbit.vhd the current project. Then click  to compile.
3. Enter File, New, Wave Form File menus to create simulation file to test eqbit design.
4. Click the right moouse button while pointing inside the Waveform Editor window, then select Enter Nodes from SNF..., then , , and . The Waveform editor window should appear as below:
5. Modifying the grid size of the Wave Form file can increase or decrease the time between signal changes. Select Options, Grid Size... and give a grid size of 20ns. The input signals will now change every 20ns. so that more of the possible input values can be examined.
6. Click on the  to select y. Then click on  to enter the waveform. The wave for input y should change or Count Every 20 ns and be multiplied by 4, so it changes every 80 ns. Repeat this step for inputs x Multiplied by 2 and input e Multiplied by 1. 
7. With inputs x, y, e with waveforms, click  to save the waveform file and start the simulation. The resulting Waveform Editor window should appear as below: 

Implementing and Simulating the eq4 design

1. Enter the eq4 file by copying from a browser or typing it in. In MAX+plus II enter File, New, Text File from the menus and enter the design. Save as eq4.vhd.
2. Click  to make eq4.vhd the current project. Then click  to compile.
3. Enter File, New, Wave Form File menus to create simulation file to test eq4 design.
4. Click the right button inside the Waveform Editor window, then select Enter Nodes from SNF..., then , , and .
5. To set inputs b3, b2, b1, b0 at the same time, in the Waveform editor window, move the pointer to the right of , the row should darken when selected, then drag down to select b2, b1, b0 also. The Editor window should appear as below:
6. Click right button and select Enter Group..., then  to group b[3..0] inputs together. Set the Radix to BIN.
7. Do the same for inputs a3, a2, a1, a0.
8. Click on the b[3..0] input to select, then click on  to enter the waveform. The wave should change every 100 ns. and be multiplied by 2, so it changes every 200 ns. Do the same for a[3..0] but multiply by 1. The Waveform Editor window should appear as below with b[3..0] selected: 
9. Click  to save the waveform file and start the simulation. The resulting Waveform Editor window should appear as below. The line at 100 ns. is the point where  input a[3..0] changed from 0000 to 0001. Click  to move from one change to the next to determine the delay from the input change to the change in output equal. The output equal change occurs at 111.5 ns., the difference between 111.5ns. and 100ns. is the propagation delay for the eq4 design, 11.5ns.

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Homework 3

Bit Comparator
A similar design to that of the laboratory equality operation is the complete comparator which yields greater, less, and equality. As in the laboratory, a single bit comparator should first be designed, implemented, and tested then a multiple bit comparator can be designed based upon the single bit comparator. The bit comparator compares two input bits, a and b, and the result of a lower bit comparison encoded in inputs x_i and y_i to produce outputs x_i+1 and y_i+1. The encoding of results are:

     xi yi | Encoded Result
          |                
     0  0 |   a = b
     0  1 |   a < b
     1  0 |   a > b
     1  1 |   Don't Care

Using the encoding yields a truth table below. An example of its interpretation is for input 0100, the x_iy_i inputs of 00 indicate that the lower bits were all equal, the ab inputs of 01 indicate that a < b, given that lower bits were equal. An example would be where a = 011111 and b = 111111.

The Karnaugh map simplification for the bit comparator yields the outputs of x_i+1 = ab'+ax_i+b'x_i and  y_i+1 = a'b+a'y_i+by_i.

abxiyi   | xi+1  yi+1    Meaning     __________|_________________       0000    |  0    0      a=b         0001    |  0    1      a<b          0010    |  1    0      a>b       0011    |  don't care                0100    |  0    1      a<b         0101    |  0    1      a<b          0110    |  0    1      a<b       0111    |  don't care                1000    |  1    0      a>b         1001    |  1    0      a>b          1010    |  1    0      a>b       1011    |  don't care               1100    |  0    0      a=b         1101    |  0    1      a<b          1110    |  1    0      a>b       1111    |  don't care

xiyi    ab \  00    01    11    10     00 |     |     |  d  |  1 |    01 |     |     |  d  |    |      11 |     |     |  d  |  1 |     10 |  1  |  1  |  d  |  1 |       xi+1 = ab'+axi+b'xi              xiyi    ab \  00    01    11    10     00 |     |  1  |  d  |    |    01 |  1  |  1  |  d  |  1 |    11 |     |  1  |  d  |    |     10 |     |     |  d  |    |       yi+1 = a'b+a'yi+byi

The VHDL ENTITY for the bit comparator could be:

       ENTITY bitcomp IS
                 PORT( a, b, xi, yi    : IN BIT;
                                  xi1, yi1   : OUT BIT);
       END bitcomp;

Four bit comparator
The design uses four bit comparators with the lower order bit comparator feeding results into the next higher order bit comparator as in the following diagram:



The four bit comparator design is quite similar to the eq4, a VHDL ENTITY could be:

       ENTITY comp4 IS
                 PORT( a3, a2, a1, a0, b3, b2, b1, b0 : IN BIT;
                                                                   x, y   : OUT BIT);
       END comp4;

MAX+plus II

1. Part 1 - Implement and test a one bit comparator.
2. Part 2 - Implement and test a four bit comparator that is based upon the one bit comparator of Part 1.

1. Cover Page - Your name, date, and Homework 3. Staple all pages together.
2. VHDL listing or graphical design for a one bit comparator.
3. Simulation results of a one bit comparator test and observed propagation delay.
4. VHDL listing or graphical design for four bit comparator.
5. Simulation results of four bit comparator test and observed propagation delay.