Laboratory 2 and Homework 2
Introduction to Digital Design using Logic Gates

Included are laboratory and  homework assignments covering key methods and techniques for developing and implementing digital designs using logic gates. The laboratory portion will be performed during class time and cover the skills and concepts necessary for completing the homework assignment. Graphical and hardware description language design methods were covered in Laboratory and Homework 1.

Laboratory 2

Purpose
The laboratory follows each step normally used in the design and implementation of a combinational circuit using logic gates, a circuit in which the outputs are exclusively a function of the inputs.

Digital Design Methods

Digital design and implementation can be performed by a number of methods, the following details the solution to a problem using gate logic, graphical design, and hardware description language (HDL). The initial steps of each of the design methods are common to both as indicated in the design flowchart below. The implementation methods, however, differ due to the significantly different technologies used in each.. The design and implementation steps of each are listed in flowchart fashion.
Gate Network corresponding to gt(x,y)=xy' and eq(x,y)=x'y' + xy  Specification using VHDL 
USE WORK.ALL;
ENTITY ge IS
 PORT( x, y            : IN BIT;
       gt , eq         : OUT BIT);
END ge;
ARCHITECTURE behavioral of ge IS
BEGIN
 PROCESS (x, y)
 BEGIN
  gt <= x AND NOT y;
  eq <= (NOT x AND NOT y) OR (x AND y);
 END PROCESS;
END behavioral;

Implementation using Logic Gates

Design Construction

    EQUIPMENT
    1. ET-3200 Digital Design Experimenter
    2. 22 gauge wire
    3. wire stripper
    4. 7432 OR gate
    5. 7408 AND gate
    6. 7404 INVERTER gate

      7.  
    Construction is based on the gate description and uses the ET-3200 or other digital experimenter. The design requires 3 devices for the 3 logic operations AND, OR, and NOT. The steps to construct the design are outlined below.
     
  1. Derive gate description - Derived from switching function, possibly simplified algebraically or by other methods.Gate Design
  2. Determine physical devices to use - These have already been selected for you. The pin outs of each gate is given with the corresponding logic function. Note that Pin 1 can be determined by locating the notch or small indentation at the top of each device. Pin 1 is always at the upper left of the device.
  3. WIRING DIAGRAM - Connect physical devices to implement combinational logic - The following gives the necessary connections and resulting logic. The construction steps are:
    1. Place the 7404, 7408, and 7432 devices on the design area of digital experimenter. The device legs should straddle the design area channel.
    2. Connect experimenter +5 to pin 14 (Vdc), and GND to pin 7 (Gnd).
    3. Define X and Y inputs as X=SW1 and Y=SW2.
    4. Define GT and EQ outputs as GT=L1 and EQ=L2.
    5. Complete each connection.
  4. Verify operation - The design operation is defined by the switching function:
    5.     x=SW1 y=SW2 | gt(x,y)= L1    | eq(x,y)= L2
    ____________|________________|______________
      0    0    |      0         |     1
      0    1    |      0         |     0
      1    0    |      1         |     0
      1    1    |      0         |     1
     Verify operation by observing output on L1 and L2 by entering each possible input value on SW1 and SW2.

Homework 2

EQUIPMENT
  1. ET-3200 Digital Design Experimenter
  2. 22 gauge wire
  3. wire stripper
  4. Logic gates of choice
ASSIGNMENT

Using the digital design method covered in Laboratory 2, design and implement a one bit half adder. A half adder adds two bits, X and Y, producing output of a one bit sum and a one bit carry out.

TURN IN

  1. Cover Page - Your name, date, and Homework 2. Staple all pages together.
  2. State Problem - Already completed.
  3. Describe binary switching functions -  sum(x,y) and carry out(x,y). That is, complete the following table:
    4.       x    y    | sum(x,y) | carry out(x,y)
    ____________|__________|______________
      0    0    |          |      
      0    1    |          |      
      1    0    |          |     
      1    1    |          |
  4. The problem is to be implemented and specifications turned in for the method covered in Laboratory 2.
      5. Physical gates - specification is WIRING DIAGRAM of design. This may be done using the MAX+plus II Graphic Editor or other graphics package. Be certain to add pin numbers used on actual logic chips to wiring diagram. It would normally serve as a guide when wiring a logic circuit.

      To use the gates below, in Netscape, to copy:

      1. Point to the gate diagram.
      2. Click on right button.
      3. Save Image As:
      4. To make wiring connections use Paintbrush, etc.
  5. Verification of design by entering all possible inputs and record outputs by filling in the table describing the switching functions.
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