Laboratory 4 and Homework 4
Introduction to Digital Design using Field Programmable Gate Arrays

Included are laboratory and  homework assignments covering key methods and techniques for developing and implementing digital designs using FPGA (field programmable gate array). The laboratory portion will be performed during class time and cover the skills and concepts necessary for completing the homework assignment.

Laboratory 4

Purpose
The laboratory follows each step normally used in the design and implementation of a combinational circuit using a FPGA. More complex designs can be implemented with FPGA versus individual devices since either VHDL or graphical designs can be programmed directly into a FPGA with internal connections formed automatically through software, only inputs and outputs must be connected.

Digital Design Methods

Digital design and implementation has been examined for a number of methods, with the following detailing the solution to a problem using gate logic, graphical design, and hardware description language (HDL). The initial steps of each of the design methods are common to both as indicated in the design flowchart below. The implementation methods, however, differ due to the significantly different technologies used in each. The design and implementation steps of each are listed in flowchart fashion.
Gate Network corresponding to d(x3,x2,x1,x0)
Specification using VHDL corresponding to d(x3,x2,x1,x0)
USE WORK.ALL; 

ENTITY d_segment IS 
 PORT( x3, x2, x1, x0 : IN BIT; 
             d                    : OUT BIT); 
END d_segment; 

ARCHITECTURE behavioral of d_segment IS 
BEGIN 
  PROCESS (x3, x2, x1, x0) 
  BEGIN 
    d <= NOT (x3 OR (x2 AND NOT x1 AND x0) OR (NOT x2 AND x1) 
                      OR (x1 AND NOT x0) OR (NOT x2 AND NOT x0)); 
  END PROCESS; 
END behavioral;

Implementation using FPGA

Implementation using a FPGA requires the following steps after the graphical or HDL design has been verified using simulation:
  1. Determine necessary equipment.
  2. Familiarization with the equipment.
  3. Assign the FPGA device to be used for the implementation.
  4. Assign FPGA device pins to the input/output pins specified in the design.
  5. Program the FPGA.
  6. Make wire connections from FPGA input/output pins to switches, lights, display, or other input/output devices.
  7. Test the FPGA implementation outputs for all possible inputs.

EQUIPMENT

UP1 EQUIPMENT FAMILIARIZATION

The UP1 Education Board will be used to implement significant designs such as serial ports and simple CPUs. It has two FPGA devices and associated input and output areas for each. Each FPGA device can be programmed with a graphical or VHDL design of a combinational circuit. Programming the FPGA performs the same function as wiring individual logic gates as in Homework 2. Once programmed, the FPGA behaves as a set of connected logic gates forming a combinational circuit where only inputs and outputs must be physically wired externally. The FPGA used in this assignment is the EPM7128S or MAX device on the left of the UP1. The areas used in the laboratory and homework are:

Assigning FPGA Device and Pins

  1. Select the graphical or VHDL file and make it the project file by File, Project, Set Project to Current file menu.
  2. Compile the project.
  3. The FPGA device to be used can now be selected by Assign, Pin/Location/Chip... menu entry.
  4. Click the  button and select the EPM7128SLC84-7 FPGA device, click OK to complete the device assignment.
  5.  To assign pins, enter the name of the input/output parameter for the design, for example:

    6.         ENTITY d_segment IS
                 PORT( x3, x2, x1, x0 : IN BIT;
                             d                    : OUT BIT);
            END d_segment;

    has inputs of x3,x2,x1,x0 and output of d. These can be assigned to pins by entering the Node Name (x3,x2,x1,x0, or d) and selecting the corresponding Pin for that node from the list. Then click Add to add the pin assignment. Assign all the nodes then click OK. The figure at right has assigned Node Name d to Output pin 63.

  6. With pin assignments complete, compile the project again to include the pin assignments (yes, there are two compiles necessary).

Programming

Programming the FPGA requires:
  1. Make sure that the UP1 programming jumpers (the small, black header plugs just below the JAG IN labeled TD1, TD0, DEVICE, and BOARD, see figure at right) are in correct position to program the EPM7128SLC84-7 device. The jumpers should connect the pins in the top two rows of each of the four columns (labeled TD1, TD0, DEVICE, and BOARD).
  2. Connect  the ByteBlaster cable to the parallel or printer port of the computer and the UP1 JAG IN.
  3. Connect the power plug from the power adapter to the UP1 DC IN.
  4. Open the graphical or VHDL design file, use File, Project, Set Project to Current File menu entry.
  5. Make any device or pin assignments as described in Assigning FPGA Device and Pins.
  6. Compile the project.
  7. Use MAX+plus II, Programmer menu or click on . If an error message appears, examine the JTAG and FLEX menus, uncheck any Multi-device Chains. For example, the JTag should all be unchecked as at right.
  8. Click Program. The programming window should show programming progress and indicate when programming of the FPGA is completed.

Wire Connections

WARNING: Turn UP1 power OFF whenever wiring. This will help prevent electrical damage to the UP1 while making wire connections. Unplug the power transformer from the 110 volt power strip.

To prevent physical damage to the UP1, use only the 22 gauge wire supplied in PS100. There are many colors on the spools, allowing signals to be color-coded (e.g. inputs green, outputs yellow). It may be challenging to fit the the wire into the connections, especially if the wire has been bent. Try using a new, straight wire.

As noted already, pin 63 of the FPGA is connected to the d segment and the output of the function has been assigned to that pin. The inputs for (x3,x2,x1,x0) were assigned to pins (34, 33, 36, 35) in area P3 respectively in Assigning FPGA Device and Pins, these pins must now be connected by wire to an external inputs, such as the switches of MAX_SW1. Connect the leftmost MAX_SW1 switch to x3, the next to x2, and so forth for each of the four inputs. This will allow 4 bit binary numbers to be more easily entered on the switches.

Testing

Since only the d segment is being controlled, it should be OFF when a 1, 4, or 7 (0001, 0100, and 0111) is entered on the MAX_SW1 and ON for all other switch inputs. The other segments are normally ON when no wire connection exists. To test, enter each digit from 0-9 in binary (0000-1001) on the MAX_SW1 switch to verify that the design is functioning correctly.

Homework 4

EQUIPMENT
  1. ByteBlaster Cable
  2. UP 1 Education Board
  3. 22 gauge wire
  4. wire stripper
ASSIGNMENT
Design and implement all functions (a, b, c, d, e, f, g) for a 7-segment display hexadecimal digits (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, E, and F).
TURN IN
  1. Cover Page - Your name, date, and Homework 4. Staple all pages together.
  2. State Problem - Already completed.
  3. Describe switching functions for a, b, c, d, e, f, g using truth table, one-set, etc. Combine all functions, a-g, into a single design so that the entire segment will show the correct output for inputs on the MAX_SW1.
  4. Simplify using Karnaugh maps.
  5. VHDL (recommended) or graphical design listing. The VHDL input/output definition would be similar to:

    6.         ENTITY segment7 IS
                     PORT( x3, x2, x1, x0    : IN BIT;
                                 a, b, c, d, e, f, g : OUT BIT);
           END segment7;
  6. Verify by demonstrating operation to instructor. All team members should be present. Demonstration can be performed before or after assignment due date as scheduling permits.
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