Laboratory 1 and Homework 1
Introduction to Digital Design

• Laboratory 1
• Digital Design Methods
• Implementation Instructions using Graphic Design
• Simulation Instructions with MAX+plus II
• Implementation Instructions using VHDL
• Homework 1
• Installing MAX+plus II

Laboratory 1

Purpose
The laboratory follows each step normally used in the design and implementation of a combinational circuit, a circuit in which the outputs are exclusively a function of the inputs. For comparison and to cover the methods used throughout this course, the same circuit will be implemented in three ways, 1) hand wiring gate devices that implement AND/OR/NOT logic together on an electronics designer (Laboratory 2 and Homework 2), graphical design with gate devices that specify AND/OR/NOT logic and simulate the implementation, and 3) using a hardware description language to specify and simulate the implementation.

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Digital Design Methods

Digital design and implementation can be performed by a number of methods, the following details the solution to a problem using gate logic, graphical design, and hardware description language (HDL). The initial steps of each of the design methods are common to both as indicated in the design flowchart below. The implementation methods, however, differ due to the significantly different technologies used in each.. The design and implementation steps of each are listed in flowchart fashion.

2. Describe switching function - The definition of a greater and a equal bit comparator can be given in the following truth table or switching functions gt(x,y) and eq(x,y):

 x y | gt(x,y)=  | eq(x,y)= 
 ____|_x > y   __|_x == y_____
 0 0 |      0    |     1
 0 1 |      0    |     0
 1 0 |      1    |     0
 1 1 |      0    |     1

One-set
gt(x,y)=one-set(2)
eq(x,y)=one-set(0,3)
Switching Expressions
Sum of Products
gt(x,y)=xy'
eq(x,y)=x'y'+xy
Sum of minterms
gt(x,y)=m₂ = S m(2)
eq(x,y)=m₀+m₃ = S m(0,3)
Product of Sums
gt(x,y)=(x+y)(x+y')(x'+y')
eq(x,y)=(x+y')(x'+y)
Product of Maxterms
gt(x,y)=M₀*M₁*M₃ = P M(0,1,3)
eq(x,y)=M₁*M₂ = P M(1,2)

Gate Network corresponding to gt(x,y)=xy' and eq(x,y)=x'y' + xy	Specification using VHDL
	USE WORK.ALL; ENTITY ge IS  PORT( x, y       : IN BIT;        gt , eq    : OUT BIT); END ge; ARCHITECTURE behavioral OF ge IS BEGIN  PROCESS (x, y)  BEGIN   gt <= x AND NOT y;   eq <= (NOT x AND NOT y)           OR (x AND y);  END PROCESS; END behavioral;

 4. Gate wiring or simulation - The three available methods of implementing the solution are the physical logic gate method in Laboratory and Homework 2 Implementation using Logic Gates, the graphical designer is in section  Implementation Instructions using Graphic Editor with MAX+plus II, and the HDL method is in section Implementation Instructions using VHDL with MAX+plus II.

Implementation Instructions using Graphic Editor with MAX+plus II

1. Start  MAX+plus II.
2. From menu enter File/New and select Graphic Editor file as to the right. 
3. In Graphic Editor window click right mouse button, select Enter Symbol.
4. Select Symbol Library maxplus2\max2lib\prim\*  as below (double click).

Select Symbol Library maxplus2\max2lib\prim\*	Enter Symbol and2 for an AND gate  with 2 inputs.

5. Enter Symbol and2 for an AND gate with 2 inputs as in the above and click OK.
6. The should appear in the Graphical Editor window. Repeat steps 3-5 to place or2, not, input, and output symbols into the editor window. The window should appear as:
7. Click on any symbol to select to move, copy, etc. Make the following number of symbols:
• 3 and
• 2 not
• 2 input
• 2 output
• 1 or
8. Connect or wire gates together by moving the mouse pointer to a connection point when the pointer changes to a + symbol. Hold the left mouse button down and move to the other connection point.
9. Connect to an existing wire by moving over the wire until the pointer changes to a + symbol, hold the left mouse button and move to the connection point. If the wires are connected it should appear as to the right (in red).
10. Edit pin name by clicking on the symbol, for example to edit the input, click the right mouse button to open a menu, and select Edit pin name. Change the names of the output and input as in the figure below.
11. Make all the connections and pin name changes consistent with the figure at right.
12. From menu save by File/Save as: graphicge.gdf
13. From menu enter File/Project/Set Project to Current File
14. From menu enter File/Project/Save and Compile.  If there are any missing connections they will be reported by the compiler. Click on reported errors to have the offending gate connection displayed in the Graphic Editor.
15. After errors are corrected operation of  the design can be simulated as in the following section on  Simulation Instructions with MAX+plus II .

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 Simulation Instructions with MAX+plus II

1. From menu enter MAX+plus II/Waveform Editor and you should see this window: 
2. Point inside Waveform Editor window, click right mouse button to open menu, select Enter nodes from SNF...
3. Click  button then   to edit all nodes. The Enter nodes from SNF window should appear as: 
4. Click OK.
5. All nodes should be listed in the Waveform editor. Click on the then on  from the access toolbar on left for modifying the input signals. In the Overwrite Count Value window for y input click OK. This will generate a wave form for the y input that is both false (logic 0) and true (logic 1).
6. Repeat the above for input x. In the Overwrite Count Value window, change which will double the time the x input is true or false.
7. To size the Waveform Editor window click on  from the toolbar. The Waveform Editor window should appear as: 
8. File/Save to save the waveform file under the extension name scf.
9. From menu enter MAX+plus II/Simulator/Start/Open SCF or by clicking  on toolbar to run and view results of simulation.
10. From menu enter View/Fit in Window to view complete simulation. The first figure below is of the Simulator and the second figure is of the actual simulation. Verify that the results for gt and eq agree with the following truth table for switching functions gt(x,y) and eq(x,y). For example, after 307.5 ns. input x = 1, input y =1, output gt = 0, and output eq = 1 which agrees with the truth table.

 x y | gt(x,y)=  | eq(x,y)= 
 ____|_x > y   __|_x == y_____
 0 0 |      0    |     1
 0 1 |      0    |     0
 1 0 |      1    |     0
 1 1 |      0    |     1

11.  At this point, assuming that the simulation verified the design operation, the hardware description could be programmed into a FPGA (Field Programmable Gate Array). This will be done in later assignments.

Implementation Instructions using VHDL with MAX+plus II

1. Start  MAX+plus II.
2. From menu enter File/New.

Select Text Editor file	Enter the program

3. From menu save by File/Save as: ge.vhd
4. From menu enter File/Project/Set Project to Current File
5. From menu enter MAX+plus II/Compiler/Start or by clicking  from the toolbar then Start.
6. Any errors will be listed, clicking on an error message will open the text editor to the offending line. Repeat compilation until errors are corrected.
7. After errors are corrected, operation of  the design can be simulated by following the same instructions in section Simulation Instructions with MAX+plus II.

Homework 1

Turn in

1. Cover Page - Your name, date, and Homework 1. Staple all pages together.
2. State Problem - Already completed.
3. Describe switching functions -  sum(x,y) and carry out(x,y), that is complete the following:

      x    y    | sum(x,y) | carry out(x,y)
    ____________|__________|______________
      0    0    |          |      
      0    1    |          |      
      1    0    |          |     
      1    1    |          |

4. The problem is to be implemented and specifications turned in for each of the 2 methods covered in Laboratory 1.
1. Graphic description - specification is Graphic Editor print listing.
2. HDL description - specification is program listing.
5. Verify operation for each of the 2 methods.
1. Graphic design by Waveform Editor simulation. With the Waveform Editor window opened, it can be printed through the File/Print menu.
2. HDL design by Waveform Editor simulation. With the Waveform Editor window opened, it can be printed through the File/Print menu.

Installing MAX+plus II

1. With the CDROM from the text in the drive, use the Start, Run, menu and file D:\PC\MAXPLUS2\Install.exe to start the installation program, assuming the CDROM drive is D: drive. Follow the directions for installation.
2. To enable MAX+plus II features and applications, you must enter your authorization code with the Authorization Code command (Options menu). When you use MAX+PLUS II for the first time, the Authorization Code dialog box will display a Software Guard ID that starts with the letter "S". To obtain an authorization code, make a note of this ID number, go to the student registration page on the Altera world wide web site, and follow the instructions given there. After completing the instructions and submitting your ID and authorization code will be emailed back. The student registration page is located at www.altera.com/maxplus2-student.
3. If you purchase the University Program 1 digital trainer used for several of the homeworks and available directly from Altera, you will need to install a software update. See www.altera.com/html/univ/univ-update_success.htmlfor the update.