Laboratory 9 and Homework 9
AU - Arithmetic Unit of the CPU

Laboratory 9

The CPU of a computer is generally divided into at least four components, the control unit which performs the fetch/execute cycle, the bus unit which controls access to the data and address bus, internal registers for temporary storage, and the arithmetic/logic unit (ALU) that performs arithmetic and logical operations. The following laboratory focuses on the arithmetic unit (AU) described in the text Section 10.3 and illustrated in Figure 10.12 of the text. The homework assignment is to design and implement an AU. The AU will be tested by performing the arithmetic for a simple calculator.

Full Adder

The text describes several one bit full adders including one based on two half adders such as those implemented in Home Work 1. A three bit full adder was implemented in Home Work 5. See Figure 10.3 page 281 for details. Also described in the text is the carry-ripple adder (Figure 10.2) implemented by cascading the carry out bit of one full adder to the carry in of the next. This method allows large adders to be easily implemented but suffers from a linear increase in propagation delay as the number of bits in the operands increase.

Arithmetic Unit

The text also describes in Section 10.3 the details of an arithmetic unit based upon a full adder of n bits. The AU given is capable of five arithmetic operations, add, subtract, add with carry, complement, and increment. The AU has inputs of two operands, an operation code, and a carry in bit. The output is the operation results that include flags indicating whether the result is zero, the carry out, whether overflow occurred, and the sign of the result. The following lists the key points of the AU.

Adder - As noted, the 8 bit adder can be implemented based upon 8 cascaded full bit adders. The text gives several designs in Figure 10.3 page 281.

Multiplexer - The design given in the text requires an 8 input multiplexer to select inputs to the adder. You may use one provided in the MAX+plus II environment. The COMPONENT definition is:

zero - The zero bit can be determined by taking the NOR of all bits of the result, z in the text example. A bitwise NOT result most easily done by first ORing all bits then NOT the result. Note that the expression must be fully parenthenized to be evaluated correctly.

overflow - The ovf bit is determined by forming the XOR of the carry out of  the two most significant bits, bit 6 and 7.

sign - The sign bit is the most significant bit of the result.

Operations - The AU can perform 5 operations that are encoded as 3 bit codes in Table 10.4 page 298 of the text. For example, the operation code 001 instructs the AU to add, with the effect z = x + y. Different operations are implemented by decoding the operation code into three control signals, Kx, Ky, and Kmx.

Homework 9

Assignment .
  1. Implement an 8 bit full adder based upon the carry-ripple adder of Home Work 5.
  2. Implement an 8 bit AU as described in the text in Section 10.3.
  3. Test using the provided HW9 component and the HyperTerminal program that implement a simple calculator.
Files Turn In
  1. Cover Page - Your name, date, and Homework 9. Staple all pages together.
  2. Simulation of the 8 bit adder component adding 00000001 + 01111111, and 00000010 + 11111111.
  3. VHDL listing of the 8 bit adder component.
  4. Simulation of the AU component performing 00000001 + 01111111, 11111111 + 00000010, and 00000001 - 00000010.
  5. VHDL listing of the AU component.
  6. Demonstrate calculator (HW9 component) to instructor.
AU Design Implementation

Points of note:

Testing

The testing component, HW9, implements a very, very simple calculator. Operands and operations are entered from the computer keyboard and results are displayed back to the display. To keep the UP1 design simple and continue to use the HyperTerm program on the PC for data input and output, the calculator interface is very crude. To enter a calculation to add 65 + 3 enter:

  1. A             The character corresponding to ASCII code 65 decimal or 41 hexadecimal.
  2. !              Character for addition, its ASCII code is 00100001, the low three bits are 001, the AU code for +.
  3. Ctrl D      Character code 4.
  4. Any key   The character 'E' should be displayed to the HyperTerminal screen.
  5. Any key   And hexadecimal code 45 for 'E' displayed on the LEDs.
As each character is entered, the LEDs display the hexadecimal value for the operand or operation entered. Pressing the FLEX_PB1 push button will display the present state of the main FSM. The states are: Debugging

It is essential that each component, adder and AU, be thoroughly debugged before attempting to test on the UP1. Once the adder and AU component operation has been verified through simulation, the following debugging steps are appropriate with the UP1 connected to the PC serial port.

Arithmetic Unit Component Test

The following tests the AU by reading two operands and an arithmetic operator from the computer keyboard and displaying the result as a character back to the display. The operands, operator, and result are also displayed on the two 7-segment LEDs. As in Home Work 8, the serial input and output is provided using the Windows 95 terminal program named HyperTerminal. To test the AU component do the following steps:
    1. Make a new directory and copy all the VHDL files of the components used by your AU.vhd component.
    2. A test component, HW9, implements the calculator on the UP1 using your AU. Download the self expanding file HW9.exewhich contains the calcuator components.
    3. Run HW9.exe file, by default it will create a HW9 directory containing all the files except the AU.vhd.
    4. Copy your AU.vhd component to the directory containing HW9 files.
    5. Open HW9.vhd  file, click  to set the current project, compile the HW9.vhd component. Ignore the warnings about: Project has user pin assignments but has never been compiled before.
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