Laboratory 5 and Homework 5
Multilevel Gate Networks

• Laboratory 5
• One Bit Full Adder
• 3-Bit Full Adder
• 3-bit Full Adder with 7-segment Output
• Homework 5
• EQUIPMENT
• ASSIGNMENT
• TURN IN

Laboratory 5

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One Bit Full Adder

1. State Problem - Implement the logic of a one bit full adder.

2. Describe switching functions - A one bit full adder produces a sum and carry out given two bits and a carry in. Complete the following:
 

x_i   y_i  cin_i     |    cout_i   sum_i
_________________|_________________
0    0    0      |
0    0    1      |
0    1    0      |
0    1    1      |
1    0    0      |
1    0    1      |
1    1    0      |
1    1    1      |


3. Simplify function - Use Karnaugh mappings and/or algebraic methods to derive a simplified function.

sumi(xi, yi, cini) =

couti(xi, yi, cini) =

4. VHDL description - Implement the simplified functions in VHDL.
 

ENTITY fulladd IS    PORT (xi, yi, cini : IN BIT;           sumi, couti : OUT BIT);   END fulladd;   ARCHITECTURE behavioral OF fulladd IS   BEGIN    PROCESS (xi, yi, cini)    BEGIN          sumi <=          couti <=    END PROCESS;   END behavioral;

5. Simulation - The method of simulating VHDL solutions were discussed in Laboratory 1 Simulation Instructions with MAX-plus II. The simulation should be used to verify that the sum_i(x_i, y_i, cin_i) and cout_i(x_i, y_i, cin_i) results are appropriate for each input, that is for (x_i, y_i, cin_i)input of (0, 1, 1) produces an output of sum_i = 0 and cout_i = 1. The simulation results would appear as below for all possible input values of x_i, y_i, cin_i.

3-Bit Full Adder

The hierarchical block diagram above should help in translating to VHDL, such as determining what are the inputs, outputs, and internal signals. An example can help. The following computes:

        cin₂₁₀    1 110
          x₂₁₀      101    5
         +y₂₁₀ =   +111 = +7
  cout₂ sum₂₁₀    1 100    12

The port mapping for adding bits 0 using the one bit full adder could be:

 U0 : fulladd PORT MAP(x0, y0, c0, sum0, c1);

The 3-bit adder can be tested by simulation as in Homework 3. Group x2, x1, x0; y2, y1, y0; and s3, s2, s1, s0 as below. Given that there are 64 different additions possible, it is not necessary to simulate exhaustively.

3-bit Full Adder with 7-segment Output

Inputs:        x₂₁₀ and y₂₁₀.
Outputs:     The sum is a 4 bit result (0000-1110). To display the 4 bit result on an LED
                    requires controlling each LED segment.
Signals:       Internal signals is the sum₃₂₁₀ bits output by the 3-bit adder and input by
                    the 7-segment display.
VHDL:       A corresponding VHDL ENTITY and ARCHITECTURE definition is:
 

Program the UP1 as in Homework 4. Use the same LED pin assignments for a-g segments. For input of x₂₁₀ and y₂₁₀ use any 6 pins near the MAX-SW1 rocker switches (e.g. 34-36 and 50-52). Test using some of the same values from the earlier simulation.

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Homework 5

1. ByteBlaster Cable
2. UP 1 Education Board
3. 22 gauge wire
4. wire stripper

Part 1 - Design (complete truth table and simplified function) and implement in VHDL or graphically a 1-bit full adder. The adder output should be a sum bit and the carry out bit. The design should be simulated only.

Part 2 - Design and implement in VHDL or graphically a 3-bit full adder. The adder output should be four bits consisting of the three sum bits and the final carry out bit. The design should be simulated.

Part 3 - Implement the 3-bit full adder of Part 2 on the UP1. The implementation should input two 3-bit binary numbers from six switches and output the 4-bit result to a 7-segment display.

1. Cover Page - Your name, date, and Homework 5. Staple all pages together.
2. VHDL (recommended) or graphical design listing of Parts 1 and 2.
3. Simulation of Part 1 and 2.
4. Verify UP1 implementation by demonstrating operation of Part 3 to instructor. All team members should be present. Demonstration can be performed before or after assignment due date as scheduling permits.