a. For the following signal values, determine the corresponding logic values for the positive and for the negative logic.2. (2 pts) Show a CMOS circuit that implements the following function for positive logic.i. 1.0 Vb. For a module with inputs x1 and x0 and output z you have performed the following set of voltage measures (all in volts). Determine the logic operation implement for positive and negative logic by completing the tables at right.
ii. 4.5 V
iii. 2.0 V
iv. -1.0 V
Voltages
x1 x0 | z
0.3 0.2 | 0.5
0.3 4.5 | 4.4
4.5 0.2 | 4.4
4.5 4.5 | 0.2Positive
x1 x0 | z
|
|
|
|Negative
x1 x0 | z
|
|
|
|
x1 x0 | z3. (2 pts) Given the voltage waveform for a gate with inputs x and y and output z below:
0 0 | 0
0 1 | 1
1 0 | 0
1 1 | 0

a. What positive logic operation (i.e. LOW = 0, HIGH = 1) is implemented? What negative logic operation (i.e. LOW = 1, HIGH = 0) is implemented?4. (1 pt) What is the rise and fall times for the gate output z depicted in the waveform of Question 3?
b. What is the propagation delay for this gate (i.e. tpHL and tpLH)?
5. (8 pts)
A) For
the gate diagram below, compute the fan-in and
fan-out of
each CMOS gate using the text table on page 75.
i. NOT
ii. AND2
iii. OR3
iv. AND4

D) In the following, assuming that A=True, B=False,
C=True, D=False, S0=False, S1=True, S2=False, and S3=False, what is Z?
E) What are the necessary values of S0, S1, S2, and
S3 for Z=C?