Chapter 8 Notes

8.1 Canonical Form of Sequential Networks

Finite State Machines (as a sequential network) hold the present state in memory and compute the next state and output using combinational logic. The input to the next state computation is the present state and any inputs. A modulus counter represents the simplest FSM since it has no inputs, the next state depends completely on the present state. For example, a Mod-5 counter FSM counts 0, 1, 2, 3, 4, 0, 1, ... The general architecture of an FSM is the following: the architecture consists of Compute Next State that uses the Present State to determine which will be the next state to enter. The Clock input serves to synchronize the FSM operation into discrete points of state change.

It is important to understand the role of the clock in coordinating the operation of the FSM. As the following diagram illustrates, the Next State computation is (must be) completed when the clock pulse occurs. The clock is active on the rising edge in this example meaning that all changes to the memory occur on the rising clock edge. The Next State becomes the Present State on the active clock edge, meaning the count changes.
 

FSM Architecture and Execution Diagram of Mod 5 Counter
Mealy Machine
Moore Machine
Mealy Machine - Output depends upon Present State and Input
Moore Machine - Output Only depends upon Present State

8.2 High-level and Binary Implementations

Actual FSM implementation in hardware requires that all inputs, outputs, and states be encoded into a binary representation. For the Mod-5 FSM the high level graphical representation and binary encoding of state and output are:
 

The high-level representation with binary encoding of the Mod-5 counter and state tables are:
 
Output:         z(t) element of {000, 001, 010, 011, 100} 
State:            ps(t) element of {ps2, ps1, ps0}, psi element of {0,1} 
Initial State:   ps(0) = (0,0,0) 

Transition      ns0 = ps2'*ps0' 
and Output    ns1 = ps1'*ps0+ps1*ps0' 
Functions:      ns2 = ps1*ps0 
                     z(t) = (ps2,ps1,ps0)

High-level

PS|         
A | B/0
B | C/1
C | D/2 
D | E/3           
E | A/4      
  |NS/Output
Binary encoded
  PS |
ps210|ns210/z210    
  000|  001/ 000
  001|  010/ 001
  010|  011/ 010
  011|  100/ 011
  100|  000/ 100 
     |   NS/Output
The derivation of the transition function (the function that determines the next state) is based upon the encoding for the present and next states only, since there is no input. The output of the Mod 5 counter z=(z2, z1, z0) is the present state encoding directly so no additional logic is needed to produce the output. There are three next state variables for the encoding, ns2, ns1, ns0 and each is based upon the three present state variables ps2, ps1, and ps0 (can represent up to 23 or 8 states). Using combinational logic techniques the minimal expression for each next state variable can be determined as below. For example, ns0 is determined by the function ns0(ps2, ps1, ps0) = ps2' * ps0' as determined using Karnaugh maps.
   Present      Next
ps2 ps1 ps0| ns2 ns1 ns0
  0   0   0|  0   0   1
  0   0   1|  0   1   0
  0   1   0|  0   1   1
  0   1   1|  1   0   0
  1   0   0|  0   0   0
  1   0   1|  d   d   d
  1   1   0|  d   d   d
  1   1   1|  d   d   d   
Present/Next State Table
  \ ps1 ps0      
ps2\00 01 11 10 
  0| 0| 0| 1| 0|
  1| 0| d| d| d|

   ns2 = ps1*ps0
   z2 = ps2
  \ ps1 ps0             
ps2\00 01 11 10 
  0| 0| 1| 0| 1|
  1| 0| d| d| d|

   ns1 = ps1'*ps0+ps1*ps0'
   z1 = ps1
  \ ps1 ps0
ps2\00 01 11 10 
  0| 1| 0| 0| 1|
  1| 0| d| d| d|

   ns0 = ps2'*ps0'
   z0 = ps0

8.3 D Flip-Flop - Flip-flops can serve as memory for the FSM architecture. The D-FF or Data Flip-Flop can store one data bit, either a 0 or a 1. For synchronization, flip-flops must be clocked, inputting new D data only on an active clock pulse. The excitation table and graphical representation of the D-FF is:

D-FF Excitation Table
Clk       D|Q        
Inactive  x|No Change 
Active    0|0
Active    1|1
D-FF with Preset and Clear

PreSet Clear Clk       D|Q 
0       1    x         x|1
1       0    x         x|0
1       1    Inactive  x|No Change 
1       1    Active    0|0
1       1    Active    1|1
Data Flip-Flop Excitation, Graphic Representation, MAX+plusII D-FF Symbol, and Preset/Clear D-FF table
The D-FF and other flip-flops are clocked or  edge-triggered, meaning that the input can change the output only on an active clock edge. The timing characteristics of the D-FF can be seen in the below diagram. Note that D is input only on the active clock edge. Q changes after some tp following the active clock edge.
 
D-FF Timing Behavior with Leading Active Edge
8.6 Design of Canonical Sequential Networks (Combinational Logic) - The D-FF is often used in FSM due to its simplicity as a memory device. The implementation of the Mod 5 counter using D-FFs requires solving for the next state variables ns2, ns1, ns0 as in the above Present/Next State Table. Note that the states have been encoded, with 5 states the binary encoding requires at least 3 binary digits. Each of the three digits requires a D-FF to hold the state or value of that digit, hence three D-FFs are required. Implementations in VHDL and using discrete gates for the combinational logic to compute the next state are below. Note in the simulation that the Reset = 0 forces the D-FFs to 0  (State A), when Reset = 1 the D-FF changes based upon the D input and Clock.
 
ENTITY ch8dff IS 
 PORT( Clock, Reset  : IN BIT; 
       ps2, ps1, ps0 : OUT BIT); 
END ch8dff; 

ARCHITECTURE structural OF ch8dff IS 
-- The dff is a D-FF with asynchronous Clear and Preset when 0 input 
 COMPONENT dff PORT (  D, CLK, CLRN, PRN : IN  BIT ; 
                                         Q : OUT BIT);
 END COMPONENT; 

 SIGNAL ips2, ips1, ips0        : BIT;                  -- Internal ps
 SIGNAL ns2, ns1, ns0           : BIT; 
 SIGNAL ONE, ZERO               : BIT; 
 BEGIN 
  ZERO <= '0';   ONE <= '1';                            -- Constant 0 and 1 

  -- Transition      ns0 = ps2'*ps0' 
  -- and Output      ns1 = ps1'*ps0+ps1*ps0' 
  -- Functions:      ns2 = ps1*ps0 
  --                 z(t) = (ps2,ps1,ps0)

  ns0 <= (NOT ips2) AND (NOT ips0);
  ns1 <= (NOT ips1 AND ips0) OR (ips1 AND NOT ips0);
  ns2 <= ips1 AND ips0;

  DFF0: dff    PORT MAP (ns0, Clock, Reset, ONE, ips0); 
  DFF1: dff    PORT MAP (ns1, Clock, Reset, ONE, ips1); 
  DFF2: dff    PORT MAP (ns2, Clock, Reset, ONE, ips2); 

  ps2 <= ips2;     ps1 <= ips1;      ps0 <= ips0;     -- Assign ps output
END structural;

Mod-5 Counter using D-FF and Combinational Logic to Generate Next State

Multiplexer Method - Using combinational logic to compute the next state often yields a design that is difficult to understand for even simple FSMs though the Mod-5 next state computation is straightforward. An easier, clearer implementation uses multiplexers, a general selector device, to provide the selection logic for next state. Since there are 5 states (0,1,2,3,4), 3 D-FFs are again required as present state memory.

On the multiplexer, the next state is the multiplexer inputs, selected by the present state, the D-FF output. To understand the architecture operation consider when the present state is 001.

  1. The input 001 is selected on each of the three multiplexers at s2s1s0 representing the present state of 001.
  2. The next state is represented as each of the multiplexer inputs at 001. The next state is 010 requiring that multiplexer number 2 at position 001 is 0, mux 1 at position 001 is 1, and mux 0 at position 001 is 0.
  3. With the present state 001 the next state is selected to be 010. The multiplexer s2s1s0 selects the present state 001, the multiplexer inputs select the next state 010.
The diagram below (note that the Clock would normally be connected but was not here for readability) divides the architecture into next and present state parts. Again, note the multiplexer inputs at 001 present state. Comparing the table of multiplexer inputs at the right of the diagram with the table derived for Present/Next state shows them to be identical. The key implication is that, using the multiplexer architecture, one can go directly from the Present/Next state table to the implementation without determining combinational logic for the computation of the next state. The reason is that the multiplexer logic already computes the next state (inputs to the multiplexer) based on the present state (the selection inputs).
 
      Present      Next
   ps2 ps1 ps0| ns2 ns1 ns0
0    0   0   0|  0   0   1   1
1    0   0   1|  0   1   0   2
2    0   1   0|  0   1   1   3
3    0   1   1|  1   0   0   4
4    1   0   0|  0   0   0   0
5    1   0   1|  d   d   d    
6    1   1   0|  d   d   d    
7    1   1   1|  d   d   d   
Present/Next State Table





Present  |Next State
State    |Multiplexer Input 
 s2 s1 s0| D2 D1 D0
  0  0  0|  0  0  1
  0  0  1|  0  1  0
  0  1  0|  0  1  1
  0  1  1|  1  0  0
  1  0  0|  0  0  0
  1  0  1|  d  d  d
  1  1  0|  d  d  d
  1  1  1|  d  d  d   
Multiplexer Inputs
Mod-5 Counter using Multiplexer/D-FF Architecture
8.11 Multiplexer Method in VHDL - The Mod-5 counter can be implemented graphically or using VHDL. The following is the implementation using a 74151 8-input enabled multiplexer and D-FFs. These devices have several inputs and outputs that are not required but must be given a fixed value of '0' or '1' for input, and be provided an output signal for unused outputs. The device descriptions are:
 
Inputs |      Outputs
Select | Enable |       
 C B A | GN     | Y  WN     
 X X X | H      | L  H
 L L L | L      | D0 D0'
 L L H | L      | D1 D1'
 L H L | L      | D2 D2'
 L H H | L      | D3 D3'
 H L L | L      | D4 D4'
 H L H | L      | D5 D5'
 H H L | L      | D6 D6'
 H H H | L      | D7 D7'
74151 8 Input Multiplexer
Description of 74151 8 Input Multiplexer (left) and D-FF Primitive (right)
The VHDL implementation follows the previous design, input is the Clock and output is the present state. The next state inputs to the multiplexer is in vector form of 0's and 1's for each of the three multiplexers, signals ns2, ns1, ns0 are the input vectors. Multiplexer output (y2, y1, y0) forms the next state, is determined by the present state (signals isp2, isp1, isp0). The multiplexer output (y2, y1, y0) is the input to the D-FFs that becomes the present state when the Clock signal pulses from low to high. Note that a Reset signal to the D-FFs was not included. The VHDL follows.
 
ENTITY ch8mux IS 
      PORT( Clock         : IN BIT; 
               ps2, ps1, ps0 : OUT BIT); 
END ch8mux; 

ARCHITECTURE structural OF ch8mux IS 
-- The dff is a D-FF with asynchronous Clear and Preset when 0 input 
  COMPONENT dff PORT (  D, CLK, CLRN, PRN : IN  BIT ; 
                                                                               Q : OUT BIT);
  END COMPONENT; 
   -- The 74151 is an 8-input multiplexer, input gn must be 0 to enable mux 
  COMPONENT f74151 PORT (c, b, a : IN BIT; 
                                                            d : IN BIT_VECTOR(7 DOWNTO 0); 
                                                           gn : IN BIT; 
                                                      y, wn : OUT BIT); 
  END COMPONENT; 

  SIGNAL ips2, ips1, ips0            : BIT; 
  SIGNAL ns2, ns1, ns0               : BIT_VECTOR(7 DOWNTO 0); 
  SIGNAL y2, y1, y0, x2, x1, x0  : BIT; 
  SIGNAL ONE, ZERO               : BIT; 
BEGIN 
  ns2 <= "00001000";                       -- Next State values for MUX 2 
  ns1 <= "00000110";                       --                                  MUX 1 
  ns0 <= "00000101";                       --                                  MUX 0 
  ZERO <= '0';   ONE <= '1';           -- Constant 0 and 1 

  Mux0: f74151 PORT MAP (ips2, ips1, ips0, ns0, ZERO, y0, x0); 
  Mux1: f74151 PORT MAP (ips2, ips1, ips0, ns1, ZERO, y1, x1); 
  Mux2: f74151 PORT MAP (ips2, ips1, ips0, ns2, ZERO, y2, x2); 

  DFF0: dff    PORT MAP (y0, Clock, ONE, ONE, ips0); 
  DFF1: dff    PORT MAP (y1, Clock, ONE, ONE, ips1); 
  DFF2: dff    PORT MAP (y2, Clock, ONE, ONE, ips2); 

  ps2 <= ips2;     ps1 <= ips1; ps0 <= ips0; 
END structural;

MOD-5 Counter in VHDL using 74151 and D-FF Components
The simulation of the implementation is given twice, once using the decimal value of the present state and the second time showing the three present state signals, ps2, ps1, ps0.
8.10 Design Using Special Gate Assignments (One-Hot) - The one-hot method gets its name from the fact that only one flip-flop is hot or outputting a 1 at a time. Each flip-flop corresponds to one state so no encoding of state is necessary. Most other methods (multiplexer, etc.) encode states into fewer flip-flops. For example, the Mod 5 counter requires 5 states, the binary state encoding used for multiplexer architecture requires 3 D-FFs, the one-hot method requires 5 flip-flops or one FF per state. Generally, binary encodings can encode 2n states using n FFs, 32 encoded states require only 5 FFs using the muliplexer architecture but 32 FFs for the one-hot method. The advantage of the one-hot method is that state is not encoded so does not need to be decoded to determine the state of the FSM (the multiplexer or combinational logic serve as the state decoders in the respective method). The Present/Next table for the one-hot Mod 5 counter is below. As illustrated by the diagram, the one-hot method requires no additional logic to compute the next state, it is determined completely by the present state.

The one additional requirement of the one-hot method is that only one flip-flop be hot at a time, including the starting state FF. To force the FSM to start in state 0, an asynchronous Reset is needed that forces a 1 into the D-FF 0, and 0 into D-FFs 1,2,3,4. This is accomplished by connecting a Reset to the PRESET of D-FF 0, and to the CLEAR of D-FFs 1,2,3,4. When the FSM is reset, only D-FF 0 is 1, the rest are 0.
 

Using the one-hot method, the state table is more easily developed by listing the next state first and determining which present state leads to the next state, the reverse order of the combinational and multiplexer method. For that reason the next state is listed first followed by the present state.
 
 
 
Next |Present    
State|State  
  1  | 0
  2  | 1
  3  | 2
  4  | 3
  0  | 4
  |  Next State   |Present State
  |  D-FF Inputs  | D-FF Outputs
NS|D0 D1 D2 D3 D4 |Q0 Q1 Q2 Q3 Q4|PS  NS = PS
 1| 0  1  0  0  0 | 1  0  0  0  0| 0  D1 = Q0
 2| 0  0  1  0  0 | 0  1  0  0  0| 1  D2 = Q1
 3| 0  0  0  1  0 | 0  0  1  0  0| 2  D3 = Q2
 4| 0  0  0  0  1 | 0  0  0  1  0| 3  D4 = Q3
 0| 1  0  0  0  0 | 0  0  0  0  1| 4  D0 = Q4
 
Mod 5 Counter using One-Hot/D-FF Architecture
ENTITY ch8one IS 
      PORT( Clock, Reset            : IN BIT; 
              ps4, ps3, ps2, ps1, ps0 : OUT BIT); 
END ch8one; 

ARCHITECTURE structural OF ch8one IS 
  COMPONENT dff PORT (  D, CLK, CLRN,PRN : IN  BIT ; 
                                                                              Q : OUT BIT); 
  END COMPONENT; 

  SIGNAL d0, d1, d2, d3, d4           : BIT; 
  SIGNAL q0, q1, q2, q3, q4           : BIT; 
  SIGNAL ONE                               : BIT; 
BEGIN 
  ONE <= '1'; 

  d0 <= q4;  d1 <= q0;  d2 <= q1;  d3 <= q2;  d4 <= q3; 

  DFF1: dff    PORT MAP (d1, Clock, RESET, ONE, q1); 
  DFF2: dff    PORT MAP (d2, Clock, RESET, ONE, q2); 
  DFF3: dff    PORT MAP (d3, Clock, RESET, ONE, q3); 
  DFF4: dff    PORT MAP (d4, Clock, RESET, ONE, q4); 
  DFF0: dff    PORT MAP (d0, Clock, ONE, RESET, q0); 

  ps4 <= q4; ps3 <= q3; ps2 <= q2;  ps1 <= q1; ps0 <= q0; 
END structural;

Mod-5 Counter using One-Hot D-FF in VHDL
Note: Q output is Present state, D input is Next state 
The simulation of Mod 5 counter shows:
  1. The Reset input when '0' holds the D-FFs to the initial state 0 state where the 0 D-FF is the only one hot or 1.
  2. Each present state signal, ps4, ps3, ps2, ps1, ps0 occurs hot in proper order.
  3. The Clock times when states changes occur.






FSMs with Inputs - The FSM implementations examined so far changed to the next state based solely on the  present state, no input was examined. The following revisits the use of combinational logic, multiplexer, and the one-hot methods for FSM implementation that have input.

8.6 Combinational Logic -  The FSM to be examined is a switchable counter that counts only even numbers from 0 through 4 when the input Even is true and  is a Mod 5 counter when Even is false. The high level graphical representation and with binary encodings for input, output, and state are given below.
 

Graphical Representation of FSM
Input:         Even(t) element of {0,1}
Output:        z(t) element of 
                      {000, 001, 010, 011, 100} 
State:         ps(t) element of {ps2, ps1, ps0}, 
               psi element of {0,1} 
Initial State: ps(0) = (0,0,0) 
Transition     ns0 = ps2'*ps0' 
and Output     ns1 = ps1'*ps0+ps1*ps0' 
Functions:     ns2 = ps1*ps0 
               z(t) = (ps2,ps1,ps0)
  |  Input
PS|Even=0 Even=1
A |B/0    C/0
B |C/1    C/1
C |D/2    E/2
D |E/3    E/3
E |A/4    A/4   
  |NS/Output
   |  Input
PS |Even=0  Even=1 
000|001/000 010/000
001|010/001 010/001
010|011/010 100/010
011|100/011 100/011
100|000/100 000/100
   |NS/Output
 
The transition table in terms of binary variables for input, present and next state is at left. The expressions for the next state variables (ns2, ns1, ns0) are simplified at right using Karnaugh maps. The implementation of these expressions in VHDL or graphical is very similar to the previous combinational logic implementation of the Mod-5 counter.
Input   Present      Next
Even ps2 ps1 ps0| ns2 ns1 ns0
  0    0   0   0|  0   0   1
  0    0   0   1|  0   1   0
  0    0   1   0|  0   1   1
  0    0   1   1|  1   0   0
  0    1   0   0|  0   0   0
  0    1   0   1|  d   d   d
  0    1   1   0|  d   d   d
  0    1   1   1|  d   d   d
  1    0   0   0|  0   1   0
  1    0   0   1|  0   1   0
  1    0   1   0|  1   0   0
  1    0   1   1|  1   0   0
  1    1   0   0|  0   0   0
  1    1   0   1|  d   d   d
  1    1   1   0|  d   d   d
  1    1   1   1|  d   d   d 
Present/Next State Table
Even\ ps1 ps0 
  ps2\00 01 11 10 
   00| 0| 0| 1| 0|
   01| 0| d| d| d|
   11| 0| d| d| d|
   10| 0| 0| 1| 1|

ns2 = Even*ps1
    +ps1*ps0
z2 = ps2
Even\ ps1 ps0 
  ps2\00 01 11 10 
   00| 0| 1| 0| 1|
   01| 0| d| d| d|
   11| 0| d| d| d|
   10| 1| 1| 0| 0|

ns1=ps1'*ps0
  + Even*ps2'*ps1'
  + Even'*ps1*ps0'
z1 = ps1
Even\ ps1 ps0 
  ps2\00 01 11 10 
   00| 1| 0| 0| 1|
   01| 0| d| d| d|
   11| 0| d| d| d|
   10| 0| 0| 0| 0|

ns0=Even'*ps2'*ps0'
z0 = ps0
 
 
Multiplexer Method - Combinational logic yields a design that is difficult to follow since it changes substantially for each design. While using multiplexers yields a simpler design it is necessary to define multiplexer inputs (which determine the next state) based in present state and FSM inputs. For the counter under consideration, there are two possible count sequences: when input is Even the sequence is 0, 2, 4, 0, ...; when input is Even' the 0, 1, 2, 3, 4, 0, 1, ... Obviously, at least some of the multiplexer inputs must include the input variable Even.

The diagram below defines the architecture (note that the Clock would normally be connected but was not here for readability) identical to the previous Mod 5 counter example except for the inclusion of the Even variable. Consider the input 010 to Multiplexer 2. Remember that Multiplexer 2 controls only bit 2 from the state encoding. When the present state is 010 the input Even must be examined. When Even is true or 1, the next state should be 100. When Even is false or 0, the next state should be 011. The Even variable determines whether D-FF 2 receives a 0 or 1. Hence state bit 2 is determined by the Even input variable. The derivation of multiplexer inputs can often be done by sight without the formal process as demonstrated in the table at the right of the diagram .
 
 

Present    |Input|     Next      Mux Inputs
ps2 ps1 ps0|     |ns2 ns1 ns0|  2  1     0   
  0   0   0|Even'|  0   0   1|  0  0     Even'
  0   0   0|Even |  0   1   0|  0  Even  0
  0   0   1|Even'|  0   1   0|  0  Even' 0
  0   0   1|Even |  0   1   0|  0  Even  0
  0   1   0|Even'|  0   1   1|  0  Even' Even'
  0   1   0|Even |  1   0   0|Even 0     0
  0   1   1|Even'|  1   0   0|Even'0     0
  0   1   1|Even |  1   0   0|Even 0     0
  1   0   0|Even'|  0   0   0|  0  0     0
  1   0   0|Even |  0   0   0|  0  0     0
  1   0   1|Even'|  0   0   0|  0  0     0
  1   0   1|Even |  0   0   0|  0  0     0
  1   1   0|Even'|  0   0   0|  0  0     0
  1   1   0|Even |  0   0   0|  0  0     0
  1   1   1|Even'|  0   0   0|  0  0     0
  1   1   1|Even |  0   0   0|  0  0     0
 

Deriving Multiplexer Input Expressions
In general the next state is the multiplexer input, selected by the present state. The multiplexer input depends upon the present state and input. The following expressions define the each multiplexer input for each present state.

Mux2(000) = ns2(001)*Even' + ns2(010)*Even  = 0*Even' + 0*Even = 0
Mux2(001) = ns2(010)*Even' + ns2(010)*Even  = 0*Even' + 0*Even = 0
Mux2(010) = ns2(011)*Even' + ns2(100)*Even  = 0*Even' + 1*Even = Even
Mux2(011) = ns2(100)*Even' + ns2(100)*Even  = 1*Even' + 1*Even = 1
Mux2(100) = ns2(000)*Even' + ns2(000)*Even  = 0*Even' + 0*Even = 0

Mux1(000) = ns1(001)*Even' + ns1(010)*Even  = 0*Even' + 1*Even = Even
Mux1(001) = ns1(010)*Even' + ns1(010)*Even  = 1*Even' + 1*Even = 1
Mux1(010) = ns1(011)*Even' + ns1(100)*Even  = 1*Even' + 0*Even = Even'
Mux1(011) = ns1(100)*Even' + ns1(100)*Even  = 0*Even' + 0*Even = 0
Mux1(100) = ns1(000)*Even' + ns1(000)*Even  = 0*Even' + 0*Even = 0

Mux0(000) = ns0(001)*Even' + ns0(010)*Even  = 1*Even' + 0*Even = Even'
Mux0(001) = ns0(010)*Even' + ns0(010)*Even  = 0*Even' + 0*Even = 0
Mux0(010) = ns0(011)*Even' + ns0(100)*Even  = 1*Even' + 0*Even = Even'
Mux0(011) = ns0(100)*Even' + ns0(100)*Even  = 0*Even' + 0*Even = 0
Mux0(100) = ns0(000)*Even' + ns0(000)*Even  = 0*Even' + 0*Even = 0
 

Multiplexer Method in VHDL - Using VHDL, the only significant change from the Mod-5 counter is the inclusion of the Even input variable into the definition of the next state. Note in the signal assignment of ns2, ns1, ns0 below the use of the concatenation operator & to construct all inputs at one time for multiplexers 2, 1, and 0.
 

ENTITY ch8mux IS 
      PORT( Even, Clock   : IN BIT; 
                ps2, ps1, ps0   : OUT BIT); 
END ch8mux; 

ARCHITECTURE structural OF ch8mux IS 
-- The dff is a D-FF with asynchronous Clear and Preset when 0 input 
  COMPONENT dff PORT (  D, CLK, CLRN, PRN : IN  BIT ; 
                                                                               Q : OUT BIT); 
  END COMPONENT; 
   -- The 74151 is an 8-input multiplexer, input gn must be 0 to enable mux 
  COMPONENT f74151 PORT (c, b, a : IN BIT; 
                                                            d : IN BIT_VECTOR(7 DOWNTO 0); 
                                                           gn : IN BIT; 
                                                      y, wn : OUT BIT); 
  END COMPONENT; 

  SIGNAL ips2, ips1, ips0            : BIT; 
  SIGNAL ns2, ns1, ns0               : BIT_VECTOR(7 DOWNTO 0); 
  SIGNAL y2, y1, y0, x2, x1, x0  : BIT; 
  SIGNAL ONE, ZERO               : BIT; 
BEGIN 
  ns2 <= "00001" & Even & "00";                                  -- Next State values for MUX 2 
  ns1 <= "00000" & NOT Even & "1" & Even;              --                                  MUX 1 
  ns0 <= "00000" & NOT Even & "0" & NOT Even;     --                                  MUX 0 

  ZERO <= '0';   ONE <= '1';           -- Constant 0 and 1 

  Mux0: f74151 PORT MAP (ips2, ips1, ips0, ns0, ZERO, y0, x0); 
  Mux1: f74151 PORT MAP (ips2, ips1, ips0, ns1, ZERO, y1, x1); 
  Mux2: f74151 PORT MAP (ips2, ips1, ips0, ns2, ZERO, y2, x2); 

  DFF0: dff    PORT MAP (y0, Clock, ONE, ONE, ips0); 
  DFF1: dff    PORT MAP (y1, Clock, ONE, ONE, ips1); 
  DFF2: dff    PORT MAP (y2, Clock, ONE, ONE, ips2); 

  ps2 <= ips2;     ps1 <= ips1; ps0 <= ips0; 
END structural;

MOD-5 Counter in VHDL using 74151 and D-FF Components
The simulation of the above implementation is given twice, once with Even input false or 0 so that a count 0, 1, 2, 3, 4, 0, ... is generated. The second simulation is with Even input true or 1 to generate a count of 0, 2,  4, 0, 2, ...
 
Simulation of VHDL Implementation of Mod 5/Even Counter
One-Hot Method - Using the one-hot method, the state table is easier to develop by listing the next state, input and determining which present state leads to the next state, the reverse order of the multiplexer method. For that reason the next state is often listed first followed by the present state. As seen in the diagram at below left, the input expression is ANDed with the appropriate next state or D-FF output. If it is possible to reach the next state from more than one present state, all input variable and present state terms are ORed (assuming SOP form).
 
Next |Input|Present
State|     |State 
  1  |Even'| 0
  2  |Even | 0 
  2  | d   | 1
  3  |Even'| 2
  4  |Even | 2
  4  | d   | 3
  0  | d   | 4
     Next State   |Input|Present State
     D-FF Inputs  |     | D-FF Outputs
NS|D0 D1 D2 D3 D4 |     |Q0 Q1 Q2 Q3 Q4|PS  NS = PS*Input
 1| 0  1  0  0  0 |Even'|1  0  0  0  0 | 0  D1 = Q0*Even'
 2| 0  0  1  0  0 |Even |1  0  0  0  0 | 0  D2 = Q0*Even
 2| 0  0  1  0  0 | d   |0  1  0  0  0 | 1       + Q1
 3| 0  0  0  1  0 |Even'|0  0  1  0  0 | 2  D3 = Q2*Even'
 4| 0  0  0  0  1 |Even |0  0  1  0  0 | 2  D4 = Q2*Even 
 4| 0  0  0  0  1 | d   |0  0  0  1  0 | 3       + Q3
 0| 1  0  0  0  0 | d   |0  0  0  0  1 | 4  D0 = Q4
ENTITY ch8one IS 
      PORT( Even, Clock, Reset      : IN BIT; 
                 ps4, ps3, ps2, ps1, ps0 : OUT BIT); 
END ch8one; 

ARCHITECTURE structural OF ch8one IS 
  COMPONENT dff PORT (  D, CLK, CLRN, 
                                                 PRN : IN  BIT ; 
                                                   Q : OUT BIT); 
  END COMPONENT; 

  SIGNAL d0, d1, d2, d3, d4           : BIT; 
  SIGNAL q0, q1, q2, q3, q4           : BIT; 
  SIGNAL ONE                               : BIT; 
BEGIN 
  ONE <= '1'; 

  d0 <= q4; 
  d1 <= q0 AND (NOT Even); 
  d2 <= (q0 AND Even) OR q1; 
  d3 <= q2 AND (NOT Even); 
  d4 <= (q2 AND Even) OR q3; 

  DFF1: dff    PORT MAP 
                     (d1, Clock, RESET, ONE, q1); 
  DFF2: dff    PORT MAP 
                     (d2, Clock, RESET, ONE, q2); 
  DFF3: dff    PORT MAP 
                     (d3, Clock, RESET, ONE, q3); 
  DFF4: dff    PORT MAP 
                     (d4, Clock, RESET, ONE, q4); 
  DFF0: dff    PORT MAP 
                     (d0, Clock, ONE, RESET, q0); 

  ps4 <= q4; ps3 <= q3; ps2 <= q2; 
  ps1 <= q1; ps0 <= q0; 
END structural; 
 

Mod-5/Even Counter using One-Hot/D-FF Architecture
Simulation of One-Hot Mod-5/Even Counter


Other Flip-Flops - The text discusses the use of the SR-FF (Set Reset), the JK-FF, and the T-FF (Toggle). Generally, the D-FF is preferable for FSM implementations since there is only a single input (D the data) resulting in fewer Karnaugh maps, etc. to solve. Further, the D-FF is most generally used also in the multiplexer and one-hot methods. The following presents excitations tables for the SR-FF and JK-FF, and produces a combinational logic solution for the Mod-5/Even counter.

Set-Reset Flip-Flops - The standard excitation table of the simple SR-FF is at left, the SR-FF primitive available in MAX+plus II with asynchronous Clear and Preset description is at right:
 

S R Clock   |    Q    
x x Inactive|No Change       
0 0 Active  |No Change
0 1 Active  |    0
1 0 Active  |    1
1 1 Active  | Illegal
SR-FF Excitation Tables
:
 
 
Present |Input|Next
Q2 Q1 Q0|Even |   |R2 S2 R1 S1 R0 S0
0  0   0|  0  |001| 1 0   1 0   0 1    
0  0   0|  1  |010| 1 0   0 1   1 0
0  0   1|  0  |010| 1 0   0 1   1 0
0  0   1|  1  |010| 1 0   0 1   1 0
0  1   0|  0  |011| 1 0   0 1   0 1
0  1   0|  1  |100| 0 1   1 0   1 0
0  1   1|  0  |100| 0 1   1 0   1 0
0  1   1|  1  |100| 0 1   1 0   1 0
1  0   0|  0  |000| 1 0   1 0   1 0
1  0   0|  1  |000| 1 0   1 0   1 0
1  0   1|  0  |000| 1 0   1 0   1 0
1  0   1|  1  |000| 1 0   1 0   1 0
1  1   0|  0  |000| 1 0   1 0   1 0
1  1   0|  1  |000| 1 0   1 0   1 0
1  1   1|  0  |000| 1 0   1 0   1 0
1  1   1|  1  |000| 1 0   1 0   1 0
Present/Next State Table
    \ Q0 Even 
Q2Q1 \00 01 11 10 
   00| 1| 1| 1| 1|
   01| 1| 0| 0| 0|
   11| 1| 1| 1| 1|
   10| 1| 1| 1| 1|
R2=Q2+Q1'+Q0'*Even' 



S2=R2' by observation  
       of Present/Next Table  
z2=Q2 
    \ Q0 Even 
Q2Q1 \00 01 11 10 
   00| 1| 0| 0| 0|
   01| 0| 1| 1| 1|
   11| 1| 1| 1| 1|
   10| 1| 1| 1| 1|
R1=Q2+Q1*Even
  +Q1*Q0
  +Q1'*Q0'*Even' 

S1=R1' by observation 
       of Present/Next Table
z1=Q1
    \ Q0 Even 
Q2Q1 \00 01 11 10 
   00| 0| 1| 1| 1|
   01| 0| 1| 1| 1|
   11| 1| 1| 1| 1|
   10| 1| 1| 1| 1|
R0=Q2+Q0+Even 
S0=R0'
z0=Q0
SR-FF Use in Combinational Logic for Mod-5/Even Counter
 JK-FF - The standard excitation table of the simple JK-FF is at left (note that it differs from the SR, when both inputs are 1 it toggles the output. Since this provides an additional way to change state of the FF, using the JK-FF can lead to much simpler combinational logic designs than with the SR-FF. The JK-FF primitive available in MAX+plus II with asynchronous Clear and Preset is at right:
 
J K Clock   |    Q    
x x Inactive|No Change
0 0 Active  |No Change
0 1 Active  |    0
1 0 Active  |    1
1 1 Active  |    Q' 
JK-FF Excitation Tables
:
Note that when Q (present state) must change from 1 to 0 it can be done with J=0, K=1 or J=K=1. When Q must change from 0 to 1 it can be done with J=1, K=0 or J=K=1. Since we know the binary encoding for both present and next states, we can choose which JK inputs yield the simpler design. The following could have produced the same next state expressions and combinational logic requirements as the SR-FF but using the toggling characteristic of JK-FF, more 1's can be used for the present state to next state transition, producing a simpler next state expression.
 
Present |Input|Next
Q2 Q1 Q0|Even |   |K2 J2 K1 J1 K0 J0
0  0   0|  0  |001| 1 0   1 0   1 1
0  0   0|  1  |010| 1 0   1 1   1 0
0  0   1|  0  |010| 1 0   1 1   1 1
0  0   1|  1  |010| 1 0   1 1   1 1
0  1   0|  0  |011| 1 0   0 1   1 1
0  1   0|  1  |100| 1 1   1 1   1 0
0  1   1|  0  |100| 1 1   1 1   1 1
0  1   1|  1  |100| 1 1   1 1   1 1
1  0   0|  0  |000| 1 1   1 0   1 0
1  0   0|  1  |000| 1 1   1 0   1 0
1  0   1|  0  |000| 1 1   1 0   1 1
1  0   1|  1  |000| 1 1   1 0   1 1
1  1   0|  0  |000| 1 1   1 1   1 0
1  1   0|  1  |000| 1 1   1 1   1 0
1  1   1|  0  |000| 1 1   1 1   1 1
1  1   1|  1  |000| 1 1   1 1   1 1
Present/Next State Table
     \ Q0 Even 
 Q2Q1 \00 01 11 10 
    00| 1| 1| 1| 1|
    01| 1| 1| 1| 1|
    11| 1| 1| 1| 1|
    10| 1| 1| 1| 1|

 K2=1

     \ Q0 Even 
 Q2Q1 \00 01 11 10 
    00| 0| 0| 0| 0|
    01| 0| 1| 1| 1|
    11| 1| 1| 1| 1|
    10| 1| 1| 1| 1|
 J2=Q2+Q1*Q0
   +Q1*Even 

 z2=Q2 
    \ Q0 Even                  
Q2Q1 \00 01 11 10 
   00| 1| 1| 1| 1|
   01| 0| 1| 1| 1|
   11| 1| 1| 1| 1|
   10| 1| 1| 1| 1|
K1=Q2+Q1'+Q0+Even

    \ Q0 Even 
Q2Q1 \00 01 11 10 
   00| 0| 1| 1| 1|
   01| 1| 1| 1| 1|
   11| 1| 1| 1| 1|
   10| 0| 0| 0| 0|
J1=Q1+Q2'*Even
  +Q2'*Q0 

z1=Q1
    \ Q0 Even 
Q2Q1 \00 01 11 10 
   00| 1| 1| 1| 1|
   01| 1| 1| 1| 1|
   11| 1| 1| 1| 1|
   10| 1| 1| 1| 1|
K0=1
    \ Q0 Even 
Q2Q1 \00 01 11 10 
   00| 1| 0| 1| 1|
   01| 1| 0| 1| 1|
   11| 0| 0| 1| 1|
   10| 0| 0| 1| 1|
J0=Q0+Q2'*Q0'*Even' 
z0=Q0
JK-FF Use in Combinational Logic for Mod-5/Even Counter