Chapter 4 Notes

1. 4.2 Description and Characteristics of Gate Networks
• Netlist or Tabular representation - Used by most computer based design tools (including MAX+plusII) to represent implementation. The following diagram (Figure 4.5 of text) is equivalent to the netlist given below.


 

Gate |Type |Inputs|Output       From  | To
A    |OR2  |A1    | A3           x0   | A1
     |     |A2    |              x1   | A2
B    |AND2 |B1    | B3           A3   | B1
     |     |B2    |              x2   | B2
C    |OR2  |C1    | C3           x2   | C1
     |     |C2    |              x3   | C2
D    |NOT  |D1    | D2           B3   | D2
E    |OR3  |E1    | E4           D2   | E1
     |     |E2    |              C3   | E2
     |     |E3    |              x4   | E3
F    |NOT  |F1    | F2           E4   | F1

• VHDL equivalent representation of the netlist.

 

ENTITY Fig4_5 IS     PORT( x4, x3, x2, x1, x0 : IN BIT;                                        z : OUT BIT); END Fig4_5; ARCHITECTURE behavioral of Fig4_5 IS     SIGNAL A3, B3, C3, D2, E4, F2; BEGIN      PROCESS (x4,x3,x2,x1,x0)      BEGIN         A3 <= x0 OR x1;         B3 <= A3 AND x2;         C3 <= x2 AND x3;         D2 <= NOT B3;         E4 <= B3 OR C3 OR x4;         F2 <= NOT E4;         z <= F2;      END PROCESS; END behavioral;

2. 4.3 Sets of Gates
1. Universal Sets - Since any combinational system can be described using AND, OR, and NOT operations, they form a universal set. Any equivalent set of operations is also universal. For example {XNOR, OR} is shown to be universal in the following by showing AND and NOT operations using only XNOR, OR, and constants 0 or 1. First NOT x is shown to be equivalent to 0 XNOR x, then x AND y is shown to be equivalent to NOT(NOT x OR NOT y). Therefore {XNOR, OR} == {NOT, AND, OR}.

x y |x XNOR y | x OR y | x NOT=0 XNOR x| x AND y = NOT(NOT x OR NOT y)
0 0 |   1     |   0    |    1          |     0
0 1 |   0     |   1    |    1          |     0
1 0 |   0     |   1    |    0          |     0
1 1 |   1     |   1    |    0          |     1

2. NAND and NOR - The NAND and NOR gates are each universal sets, hence each can be used to implement any combinational system. Many real systems such as computer CPUs and memory are implemented entirely in either NAND or NOR gates, that is {NOR} == {NAND} == {NOT, AND, OR}. The universality of NAND is shown below.

x y|x NAND y|NOT x = x NAND x|x AND y=NOT (x NAND y)|x OR y = NOT(NOT x AND NOT y) 
0 0|   1    |   1            |          0           |           0 
0 1|   1    |   1            |          0           |           1 
1 0|   1    |   0            |          0           |           1 
1 1|   0    |   0            |          1           |           1

3. 4.4 Analysis of Networks
Mixed Logic DUALS - DeMorgan's rules shows dual representation of the NAND and NOR gates that are useful for simplifying analysis and design using NAND and NOR gates. From DeMorgan's rules, the following duals are (xy)' = x' + y' and (x+y)' = x'y'. A graphical simplification can easily be done using these duals, where a circle o is interpreted as NOT. Graphically they are:
and 
NAND - The NAND network below can be converted to an AND, OR, NOT sum of products network by using the duals and noting that circles are NOTs and two NOTs in sequence cancel. The following three designs are equivalent representations. Notice that when two circles (NOTs) are on the same sequential connection, they cancel since (x')' = x. The first diagram is a NAND network, the second an equivalent mixed logic representation, and the third with cancellation of NOTs.


 NOR - A NOR network has many of the same advantages as a NAND and can also be easily converted between a AND, OR, NOT product of sums network using the dual.

 

4. 4.5 Description of Gates Using VHDL
• Behavioral representation - A behavioral  level description in VHDL of Figure 4.5 uses AND, OR, NOT and other logic operations. A behavioral description generally implements a logic expression versus implementation details (timing, loading factors, etc.). The logic expression for the corresponding VHDL behavioral level description for Figure 4.5 is: z = ((x₀+x₁)x₂)'+x₂x₃+x₄)'

 

ENTITY Fig4_5 IS     PORT( x4, x3, x2, x1, x0 : IN BIT;                                        z : OUT BIT); END Fig4_5; ARCHITECTURE behavioral of Fig4_5 IS BEGIN      PROCESS (x4,x3,x2,x1,x0)      BEGIN         z <= NOT (NOT ((x0 OR x1) AND x2) OR (X2 AND x3) OR x4);      END PROCESS; END behavioral;

• Structural representation - The structural level describes how devices are connected, necessary when using devices that are not standard logic (AND, OR, etc.) devices such as those of your own construction. Suppose that we had constructed our own AND, OR2, OR3, NOT devices (named MyAND, MyOR2, MyOR3, MyNOT), for which the following is a VHDL behavioral level description similar to that used in homeworks.
 

-- File MyAND.vhd ENTITY MyAND IS      PORT( x, y : IN BIT;                      z : OUT BIT);  END MyAND;  ARCHITECTURE behavioral of MyAND IS  BEGIN       PROCESS (x,y)       BEGIN          z <= x AND y;       END PROCESS;  END behavioral;	-- File MyOR2.vhd ENTITY MyOR2 IS      PORT( x, y : IN BIT;                      z : OUT BIT);  END MyOR2;  ARCHITECTURE behavioral of MyOR2 IS  BEGIN       PROCESS (x,y)       BEGIN          z <= x OR y;       END PROCESS;  END behavioral;
-- File MyNOT.vhd ENTITY MyNOT IS      PORT( x    : IN BIT;                      z : OUT BIT);  END MyNOT;  ARCHITECTURE behavioral of MyNOT IS  BEGIN       PROCESS (x,y)       BEGIN          z <= NOT x;       END PROCESS;  END behavioral;	-- File MyOR3.vhd ENTITY MyOR3 IS      PORT( w, x, y : IN BIT;                           z : OUT BIT);  END MyOR3;  ARCHITECTURE behavioral of MyOR3 IS  BEGIN       PROCESS (w, x,y)       BEGIN         z <= w OR x OR y;       END PROCESS;  END behavioral;

Our definitions cannot appear in a logic expression, but  are used more in the way of a function call where signal connections are parameters passed to and returned from the function execution.
 

• COMPONENT - Defines the name of a device in a library and the input/output signals, similar to a function prototype.
• PORT MAP - Serves to define signal connections to the input and output of a device (component).

 

 
 
 



Figure 4.5 can now be represented at the structural level in the following:
 

-- Fig4_5.vhd ENTITY Fig4_5 IS  PORT( x4, x3, x2, x1, x0  :  IN BIT;                                      z   : OUT BIT); END Fig4_5; ARCHITECTURE structural OF Fig4_5 IS      COMPONENT MyAND                                -- Prototype definitions.           PORT( x,y  : IN BIT; z : OUT BIT);      END COMPONENT;      COMPONENT MyOR2           PORT( x,y  : IN BIT; z : OUT BIT);      END COMPONENT;      COMPONENT MyOR3           PORT( w,x,y  : IN BIT; z : OUT BIT);      END COMPONENT;      COMPONENT MyNOT           PORT( x,y  : IN BIT; z : OUT BIT);      END COMPONENT;      SIGNAL a3, b3, c3, d2, e4 : BIT;           -- Internal connecting signals. BEGIN  A: MyOR2 PORT MAP(x0, x1, a3);         -- Signal a3 connects A: MyOR2 output to B: MyAND input.  B: MyAND PORT MAP(a3, x2, b3);  C: MyAND PORT MAP(x2, x3, c3);         -- Signal c3 connects C: MyAND output to E: MyOR3 input  D: MyNOT PORT MAP(b3, d2);  E: MyOR3  PORT MAP(d2, c3, x4, e4);  F: MyNOT PORT MAP(e4, z); END structural;

• Behavioral/Structural Differences


Behavioral descriptions are generally comprised of sequential statements within a PROCESS block. The specific purpose of PROCESS block is to denote sequential statements such as logic expressions (e.g. z <= a OR b; ). These can be thought of as operating much as a C++ program execution, sequentially.
 

Structural descriptions are not part of a PROCESS block for sequential statements. Instead all PORT MAP statements are concurrent. This is reasonable since only the structure or device connections are being described, which corresponds to the physical gate network structure. The PORT MAP statements above could be listed in any order with precisely the same results.

One artifact of the concurrent behavior is that outputs change as signals propagate through the network, hence propagation time is an implicit element of device behavior. Changing the x4-x0 inputs and measuring the z output of our network after 1ns, 5ns., 10ns, and again after 30ns. would likely see a difference at the output as the gates propagated the input change even though the x4-x0 inputs remained stable after the initial change.